Mentor Graphics announced the availability of the next-generation PADS flow with the introduction of PADS 9.0. This enhanced release adds new levels of functionality, scalability and integration, enabling designers to leverage many of Mentor’s technologies for design, analysis, manufacturing and multidisciplined collaboration. With the scalable PADS 9.0, flow users can cost-effectively design products from basic to highly complex, high-performance and dense PCBs.
New functionality includes the addition of manufacturing and collaboration tools, and powerful thermal, signal and power integrity analysis, as well as many core design entry and layout enhancements.
Consistent with PADS 9.0 scalable flow strategy, Mentor now offers a series of pre-configured PADS suites that address designer’s technology needs cost-effectively. A typical suite configuration includes:
* Design entry including DxDesigner, variant management and data import/translators from competitors’ PCB design systems.
* HyperLynx pre-and post-layout signal integrity simulation, thermal analysis and analog simulation.
* PADS layout with powerful auto-routing, high-speed rule adherence, unlimited database and layers and design reuse.
* Advanced manufacturing rules.
* 3D viewer and integration to multidisciplined collaboration solutions.
The DxDesigner tool provides complete system design capability in a single user environment. The environment integrates schematic, HDL, analog and PCB design disciplines to accelerate the design process. A 3D viewer has been introduced to the PADS flow which allows users to get a true 3D representation of their design in the PCB environment. The 3D models of components – mechanical parts, such as brackets and enclosures – can be imported to identify mechanical conflicts earlier in the design.
Several enhancements for high-speed design have been made, including routing accordion patterns with arcs, accordion keep-outs, and differential pair tuning to ensure each trace is exactly the same length. Pad stack creation has been enhanced to allow rounded and chamfered corners. New outputs have been introduced in PADS 9.0 including IPC356 netlist and a new ‘flat’ DXF file. Other enhancements include new layer visibility commands, and additional automation objects and methods.
Siemens acquires Canopus AI ASIC Design Services
News
The acquisition extends Siemens’ comprehensive EDA software portfolio with computational metrology and inspection to help chipmakers solve critical technical challenges in semiconductor manufacturing.
Read more...Aligning clocks over large distances ASIC Design Services
Test & Measurement
SkyWire technology from Microchip makes it easier to align and compare clocks within nanoseconds across geographic locations.
Read more...High-accuracy time transfer solution ASIC Design Services
Telecoms, Datacoms, Wireless, IoT
Microchip Technology recently announced the release of the TimeProvider 4500 v3 grandmaster clock (TP4500) designed to deliver sub-nanosecond accuracy for time distribution across 800 km long-haul optical transmission.
Read more...New RT PolarFire device qualifications ASIC Design Services
DSP, Micros & Memory
Microchip expands space-qualified FPGA portfolio with new RT PolarFire device qualifications and SoC availability.
Read more...Siemens’ software selected for verification and validation ASIC Design Services
Design Automation
Siemens Digital Industries Software recently announced that Veloce Strato CS and Veloce proFPGA CS have been deployed at Arm, a longtime user of Veloce, as part of its design flow for Arm Neoverse Compute Subsystems.
Read more...XJTAG launches two new Flash programmers ASIC Design Services
DSP, Micros & Memory
XJTAG has announced XJExpress and XJExpress-FPGA, a pair of Flash programmers perfect for development, debug and in-service applications.
Read more...Siemens unveils groundbreaking Tessent AnalogTest software ASIC Design Services
Design Automation
Siemens Digital Industries Software recently introduced Tessent AnalogTest software - an innovative solution that reduces pattern generation time for analogue circuit tests from months to days.
Read more...Advanced PMIC for high-performance AI applications ASIC Design Services
Power Electronics / Power Management
Microchip Technology has announced the MCP16701, a Power Management Integrated Circuit (PMIC) designed to meet the needs of high-performance MPU and FPGA designers.
Read more...MPLAB PICkit Basic ASIC Design Services
Design Automation
To make its robust programming and debugging capabilities accessible to a wider range of engineers, Microchip Technology has launched the MPLAB PICkit Basic in-circuit debugger.
While every effort has been made to ensure the accuracy of the information contained herein, the publisher and its agents cannot be held responsible for any errors contained, or any loss incurred as a result. Articles published do not necessarily reflect the views of the publishers. The editor reserves the right to alter or cut copy. Articles submitted are deemed to have been cleared for publication. Advertisements and company contact details are published as provided by the advertiser. Technews Publishing (Pty) Ltd cannot be held responsible for the accuracy or veracity of supplied material.