Quad/dual 14-bit, 125 MSps ADCs
25 November 2009
Analogue, Mixed Signal, LSI
New from Linear Technology is a family of 24 low-power 14-bit/12-bit, 125 MSps to 25 MSps, quad and dual ADCs. The flagship model is the LTC2175-14, a quad 14-bit, 125 MSps part that dissipates only 558 mW (140 mW per channel).
The LTC2175 offers signal to noise ratio (SNR) performance of 73,4 dB and spurious free dynamic range (SFDR) of 88 dB at baseband. Operating from 1,8 V analog and digital supplies, the device includes a sleep mode that reduces power dissipation to just 1 mW. Whether operating at full speed or in sleep mode, this ADC is designed to lower the power budget for high-speed multichannel designs such as multiple-input multiple-output (MIMO) WiMAX/LTE and 3G base stations, portable medical imaging and non-destructive testers.
Data is output from the LTC2175 in serial LVDS format to minimise the number of data lines. At 125 MSps, each channel outputs two bits at a time, using two lanes per ADC. At lower sample rates, a one-bit-per-channel option is available. The device includes an SPI-compatible interface that allows users to choose between a variety of data settings that reduce digital feedback. Options include a data output randomiser that reduces digital feedback, seven programmable LVDS output current levels, internal 100 LVDS output termination resistors and digital output test patterns. These settings can be programmed via SPI or hard-wired for a reduced set of operating modes.
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