Design Automation


Higher performance version of mixed-HDL simulator released

9 May 2001 Design Automation

Model Technology's powerful new version of its industry-leading HDL simulation tool, ModelSim 5.5, is aimed at today's multimillion gate ASIC and FPGA designs. The company says ModelSim 5.5 offers significant enhancements in memory utilisation, interactive debug features, testbench and regression test support, and offers substantial performance improvements for both VHDL and Verilog.

According to Model Technology, RTL simulation performance is up to two times higher for both Verilog and VHDL. Also, Verilog gate-level simulation users can benefit from a 2-4X performance improvement along with two to three times smaller memory footprints - enabling very large designs to still fit into 32 bit workstations.

"With across the board performance increases plus tremendous new functionality in debug and ease of use, ModelSim 5.5 offers an unprecedented leap in capability for our customers," said John Lenyo, Director of Marketing for Model Technology. "We have been gaining market share across all segments, and ModelSim 5.5 will enable us to reach even more designers."

ModelSim 5.5 includes many significant improvements targeted at higher productivity, including waveform compare, a new Signal Spy feature, and waveform compression. A new Waveform Compare tool offers both text reporting and an advanced graphical interface that simplifies setting up regression test environments and speeds up the debugging of design problems. Waveform Compare is fully integrated into the ModelSim environment and comes as a standard feature of ModelSim SE. It is also available as an upgrade for ModelSim EE and PE users.





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