Altera has announced its next-generation 28 nm Stratix V FPGA family, said to be the industry’s highest bandwidth FPGA. Offering up to 1,6 Tbps of serial switching capability, the FPGAs leverage a myriad of new to reduce the cost and power of high-bandwidth applications.
The Stratix V family provides up to 1,1 million logic elements (LEs), 53 Mbits embedded memory, 3680 18x18 multipliers and integrated transceivers operating up to 28 Gbps. The devices also incorporate a high level of application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty. The family includes four variants that address a broad range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets. These variants include:
* Stratix V GT, with integrated 28 Gbps transceivers targeting 100G systems and beyond.
* Stratix V GX, which supports a wide range of applications with 600 Mbps to 12,5 Gbps transceivers.
* Stratix V GS, optimised for high-performance digital signal processing (DSP) applications with 600 Mbps to 12,5 Gbps transceivers.
* Stratix V E, for ASIC prototyping, emulation or high-performance computing applications.
Stratix V GX and Stratix V GS FPGAs feature up to 66 high-performance, low-power transceivers operating up to 12,5 Gbps. Stratix V FPGAs support and meet compliance for a multitude of 3G, 6G and 10G protocols and electrical standards such as 10G/40G/100G, Interlaken and PCI Express (PCIe) Gen3, Gen2, Gen1. The devices also provide direct interoperability to 10G backplanes (10GBASE-KR) and optical modules. Stratix V GT FPGA’s 28 Gbps transceivers are designed to meet the CEI-28G specification; these 28 Gbps transceivers consume only 200 mW per channel. In addition to transceiver bandwidth, Stratix V FPGAs include a 7 x 72-bit 1600 Mbps DDR3 memory interface and LVDS channels capable of operating at 1,6 Gbps on ubiquitous I/Os.
Altera made several enhancements to the Stratix V FPGA’s core architecture to increase area and logic efficiency and system performance. A new adaptive logic module (ALM) architecture adds up to 800K additional registers in the largest device to maximise logic efficiency. The ALM architecture is optimised for heavily pipelined and register-rich designs. An enhanced embedded memory structure featuring M20K blocks offers improved area efficiency and higher performance. A variable-precision DSP block provides high efficiency and performance across multiple-precision DSP data paths, while user friendly partial reconfiguration allows designers to reconfigure part of the FPGA while other sections remain running.
Hard IP integration in the device include PCIe Gen3, Gen2, Gen1, 40G/100G Ethernet, CPRI/OBSAI, Interlaken, Serial RapidIO (SRIO) 2.0 and 10 Gigabit Ethernet (GbE) 10GBASE-R. Memory interfaces with hardened read/write paths include DDR3, RLDRAM II and QDR II+.
As announced earlier this year, Stratix V FPGAs feature the company’s embedded HardCopy blocks. This unique methodology gives Altera the ability to quickly change hardened functions within the FPGA, enabling the development of application-targeted device variants in three to six months. Embedded HardCopy blocks provide customers the equivalent of 700K additional LEs with 65% lower power compared to a soft logic implementation.
For more information contact EBV Electrolink, +27 (0)21 402 1940, [email protected], www.ebv.com
| Tel: | +27 11 236 1900 |
| Email: | [email protected] |
| www: | www.ebv.com |
| Articles: | More information and articles about EBV Electrolink |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version