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Mixed signal FPGAs aid power management
18 August 2010, Power Electronics / Power Management

Low device power consumption, low cooling requirements, efficient power management and system monitoring all contribute to the total efficiency of a system.

With increasing emphasis on efficient use of limited energy supplies and natural resources, products with the smallest impact and most efficient use of energy deliver a real competitive advantage. Management of power at the system level is a challenge faced by all system designers who grapple with a daunting set of divides between digital and analog as well as software and circuitry when they consider the best tools, practices and methodologies. An innovative methodology developed by Actel is aimed at addressing these challenges and eliminating barriers to delivering user-configurable mixed signal power management that spans software and hardware, analog and digital domains, all without the need to reprogram FPGA circuitry to implement functional changes.

Management of power-up sequencing, monitoring and trimming onboard power regulators, conditionally invoking partial or full system power-down, and managing power-down sequencing are functions often implemented using assemblies of discrete devices, but it is rare that standard devices precisely meet the exact specifications of a particular requirement due to fixed number of channels, limited voltage range and limited digital input/output (I/O) capabilities.

Designers are reluctant at times to consider custom power management solutions because of added design cycle time, cost and the need to systematically validate such a solution. This risk aversion leads inevitably to compromise, such as downgrading of the feature set to match the capabilities of available devices, or selecting parts that exceed design requirements despite performance, board space and price penalties. With the advent of mixed signal FPGA devices that integrate industry standard embedded microcontrollers, these compromises can be reduced, but new challenges arise.

Mixed signal power manager (MPM)

To address the concerns of experienced FPGA designers, embedded system designers and analog and PCB developers alike, Actel has created a new type of application specific design, called the Graphical Design Configuration methodology. This new concept separates basic circuit design from functional configuration and provides a graphical user interface (GUI) tool to configure and define application-specific functionality in a programmed, highly reliable, non-volatile Flash-based FPGA device.

The first application of the new Graphical Design Configuration paradigm is the mixed signal power manager.

MPM functionality

MPM is a user-configurable power manager that leverages the unique capabilities of Actel’s mixed signal FPGA family to deliver flexible power management. MPM functionality is configured using a standalone GUI application by loading values in on-chip non-volatile memory (NVM) without requiring changes to any of the circuitry programmed into the Actel Fusion FPGA device, so changes made to functionality do not require resimulation or reprogramming of the FPGA.

Designers can use the MPM graphical configuration tool to set rail voltage thresholds, configure power management timing, assign sequencing, define flags and set conditional functionality for up to 24 managed power supply rails. These settings can be quickly altered and reloaded using the GUI, allowing rapid hardware-based validation iteration for all selections, settings and sequencing configurations. MPM also delivers features above and beyond those available in traditional discrete devices, including persistent time-stamped data and event logging accessible via peek/poke over I²C, temperature monitoring using onboard or remote sensors and closed-loop voltage trimming using pulse-width modulation for up to eight managed rails.

Digital outputs and inputs

All digital outputs are definable via the MPM graphical configuration tool. This allows export of digital state flags for any condition or state for external monitoring use on the board. User-definable voltage thresholds for each rail can be logically combined (as AND or OR) to create custom status or health digital signals to drive indicator LEDs or switch onboard resources such as audible alarm emitters or cooling fans. These signals can also be routed off-board to shelf-level monitoring resources to enable shelf management to be aware of status, systems states and alarms. Similarly, a large number of available digital inputs allow either off-board or onboard signals, including signals from shelf-level management, to be integrated into MPM functionality and trigger power management actions such as commanding individual rail or system shut-down, all configurable using the GUI tool.

Other features

MPM features integrated closed-loop voltage trimming, using pulse-width modulation techniques on regulators that support voltage trim signals. By constantly monitoring and correcting output voltage to set values, MPM-controlled regulators maintain very precise voltages, and when the trim signal reaches its limit, configurable threshold settings can trigger an alarm or rail shut-down. Configurable, flexible voltage trimming functionality also delivers support for manufacturing test without requiring dedicated test equipment – the trimming function can force the rail to low and high range on command, enabling the reduction of test costs.

MPM also integrates on-chip or remote thermal sensing using integrated temperature monitor features. By integrating thermal monitoring, voltage monitoring, voltage trimming including manufacturing test, extensive signalling, combinatorial flag generation and extensive digital inputs, MPM delivers a compelling solution to power management challenges.

Families supporting MPM

MPM features a graphical configuration tool that allows designers to implement customised power management performance in an Actel Fusion mixed signal FPGA – and now in the SmartFusion intelligent mixed signal FPGA, featuring the ARM 32-bit Cortex-M3 processor – all without ever being required to open the Libero IDE design tool suite.

Fusion mixed signal FPGA

Fusion is the first mixed signal FPGA, delivering up to 22 analog channels that accommodate signals from –10 V to +12 V. Fusion includes up to 1 MByte of on-chip NVM, Actel’s low-power Flash FPGA fabric, built-in RC oscillator and real-time counter (RTC). Fusion is live at power-up and highly reliable – all Actel FPGAs are immune to firm errors caused by sea-level neutron or cosmic ray impact events and alpha particle events emitted by solder used in electronic packaging. Fusion also supports the embedded ARM Cortex-M1 32-bit microprocessor, enabling a single chip to deliver a complete embedded system, which, with MPM, also includes integrated power management.

SmartFusion intelligent mixed signal FPGA

SmartFusion FPGAs deliver up to 22 analog channels, eight of which can be trimmed, accommodating signals from –11,5 V to +14,4 V. The SmartFusion family builds on the foundation of Fusion, adding an evolved programmable analog capability to the performance of a 100 MHz ARM 32-bit Cortex-M3 processor, up to 512 KBytes of on-chip non-volatile memory, 64 KBytes of on-chip SRAM, a 10/100 Ethernet MAC, external memory controller, 8-channel DMA, I²C, SPI and UART interfaces, all implemented in hard gates, preserving the Flash FPGA fabric for custom design. With SmartFusion, Actel’s MPM design delivers a true single-chip power management solution.

Advantages of MPM

The Graphical Design Configuration methodology used in MPM delivers several advantages. One is the reduction in total parts count. MPM can replace multiple discrete devices with a single Fusion FPGA, integrating power management functionality into a single chip. Using SmartFusion, integration expands to include power management, a 100 MHz ARM processor, 10/100 Ethernet MAC and more, all in one low-power, high-reliability device.

Real-world designs have achieved total bill-of-materials (BOM) reductions of from 50% to 75% when integrating complex analog-to-digital and power management functions. Total parts count reductions roll directly into bottom line cost, but also deliver reduced assembly cost, lower total thermal load and lower total power consumption, while increasing board-level reliability.

MPM also allows board designs to be simplified. Board designers are constantly faced with challenging placement and layout issues, especially in boards incorporating components that touch on both the digital and analog domains. By reducing total parts count, board complexity can be reduced, PCB layers can be reduced, and total design and assembly costs can be minimised, while adding flexibility by taking advantage of the configurability delivered by the MPM graphical configuration tool. System reliability also improves as total parts count is reduced and single points of failure are eliminated.

Power consumption and thermal loading also improve with reduction in total parts count. Actel’s intrinsically low-power devices, such as Fusion, deliver reduced power consumption and enable design of products with the smallest power impact and most efficient use of energy.

While it delivers the advantages described above, the Graphical Design Configuration methodology does not prevent designers from choosing to expand system functionality using the traditional FPGA design flow. Designers can customise their designs to add functionality using Libero IDE and Actel’s extensive portfolio of IP cores. By adding functional blocks to the FPGA fabric in Libero IDE, the MPM demonstration designs described above can use configurable status flags with additional combinatorial logical elements to build complex on-chip management resources.

This flexibility also extends to embedded designers, who can add custom code running on the 100 MHz Cortex-M3 processor. Combined with programmable analog capability for analog designers, designs incorporating MPM could implement a Web server application running on the ARM Cortex-M3 processor, serving a status Web page via 10/100 Ethernet network IP integrating onboard or off-board SPI and I²C sensor device data and running a custom communication algorithm to communicate status packets and receive commands over RMII Ethernet with a management application running on a remote PC.

Available IP includes more than 50 additional IP cores from Actel, and many more from Actel IP partners. Using Actel’s graphical SmartDesign tool with MPM, digital designers can build a complete system-on-a-chip design while retaining the power management functionality of the MPM graphical user configuration tool. Embedded designers can use Actel’s SoftConsole software design environment, or software tool flows from Keil or IAR Systems to integrate embedded software projects with drivers from the Actel firmware catalogue and build executable code, then fully debug their software using the built-in debugger support.

Reference design

MPM supports up to 22 channels, but in order to illustrate its functional capabilities, a simple example design was created using MPM to control two external regulators operating at +1,5 V and +3,3 V nominal, with three digital output signals available for onboard LED and off-board status indication use. Readers interested in learning more about this reference design can access Actel’s original white paper at www.dataweek.co.za/+dw6808_p


Credit(s)
Supplied By: ASIC Design Services
Tel: +27 11 315 8316
Fax: +27 11 315 1711
Email: info@asic.co.za
www: www.asic.co.za
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Further reading:

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