NXP Semiconductors has débuted the LPC4000 family, the world’s first asymmetrical dual-core digital signal controller architecture featuring ARM Cortex-M4 and Cortex-M0 processors.
The device brings the advantage of developing DSP and MCU applications within a single architecture and development environment. With this dual-core architecture and a set of unique configurable peripherals, the device enables customers to develop a wide range of applications such as motor control, power management, industrial automation, robotics, medical, automotive accessories and embedded audio. Microcontroller designers looking for efficient ways to tackle math-intensive algorithms and DSP designers who feel constrained on peripherals stand to benefit from the architecture of the LPC4000 family.
The LPC4000 family’s Cortex-M4 processor combines the benefits of a microcontroller – integrated interrupt control, low power modes, low cost debug and ease of use – with high-performance digital signal processing features such as single-cycle MAC, single instruction multiple data (SIMD) techniques, saturating arithmetic and a floating point unit. The LPC4000 has an optimised 256-bit wide Flash memory architecture which reduces power consumption with minimum memory fetches. The device features a dual bank architecture that provides up to 1 MB Flash for safe reprogramming and flexible memory partitioning. It offers 264 KB SRAM, believed to be the largest available on any Cortex-M microcontroller.
A Cortex-M0 subsystem processor offloads many of the data movement and I/O handling duties that can drain the bandwidth of the Cortex-M4 core. This allows the Cortex-M4 to concentrate fully on crunching numbers for digital signal control applications. Having an asymmetrical dual core gives developers the benefits inherent to a one-chip solution while allowing them to more easily partition their software.
NXP’s configurable peripherals available on the LPC4000 include a state configurable timer, an SPI Flash interface and a serial GPIO interface. The state configurable timer subsystem consists of a timer array with a state machine enabling complex functionality including event-controlled PWM waveform generation, ADC synchronisation and dead-time control. The SPI Flash interface provides a seamless high-speed memory-mapped connection to virtually all SPI and quad-SPI manufacturers. NXP’s serial GPIO, available for the first time on the LPC4000, allows a developer the flexibility to interface to any non-standard serial interface or to mimic multiple standard serial interfaces (such as I²S, TDM for multichannel audio, I²C and more). Additional peripherals on certain members of the family include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware-enabled TCP/IP checksum calculation and a high-resolution colour LCD controller.
Standard features on all members of the LPC4000 family include 32 KB ROM containing boot code and on-chip software drivers, AES-128 decryption (encryption is available on some members of the family), eight-channel general-purpose DMA (GPDMA) controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400 kSps, a motor control PWM and quadrature encoder interface, four UARTs, two Fast-mode Plus I²C, I²S, two SSP/SPI, smartcard interface, four timers, windowed watchdog timer, an alarm timer, a low-power RTC with 256 Bytes of battery powered backup registers, and up to 146 general purpose I/O pins.
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