Freescale’s new MSC8157 and MSC8158 products are the next generation of the widely deployed MSC8156 DSP.
They are based on Freescale’s SC3850 core running at 1,2 Ghz, which reportedly earned the highest BDTIsimMark2000 fixed-point performance score of any DSP architecture tested to date by independent signal processing firm Berkley Design Technology, (BDTI). The MSC8157 supports a broad array of 3G and 4G wireless standards, while the MSC8158 is cost-optimised to enable more efficient and higher throughput deployments for WCDMA networks.
As the industry migrates to higher-speed, lower-latency, data-centric 3G-LTE mobile networks, OEMs increasingly demand DSPs that deliver higher throughput to address growing base station computational complexity. Freescale’s newest DSPs meet this demand with an enhanced version of its MAPLE-B baseband accelerator. The flexible MAPLE-B2 accelerator packs a high level of throughput in a small area of silicon, optimising for cost and power while providing low-latency implementations of advanced antenna processing algorithms.
The MSC8157 and MSC8158 offload many mathematical and baseband intensive tasks to the MAPLE-B2 block, freeing the processors’ six cores to handle other tasks. For example, floating-point MIMO processing is handled by the MAPLE-B2 block, improving latency over floating point DSP core implementations. The MAPLE–B2 block additionally provides OEMs a single hardware platform that supports multimode operation and allows for the adoption of additional standards with a simple software switch.
The MSC8157 delivers the peak throughput possible in 3G-LTE 20 MHz bandwidth, delivering 300 Mbps in the downlink and 150 Mbps in the uplink, with 4x4 DL and 2x4 UL MiMO, as well as various interference cancellation schemes to support hundreds of users. The DSP also supports multiple WCDMA sectors of 42 Mbps in the downlink and 11 Mbps in the uplink, together with multimode simultaneous operation of 3G-LTE and WCDMA.
Hardware accelerated features include FEC, FFT/DFT, MiMO MMSE (minimum mean square error), and MLD (maximum likelihood decoder) flexible equalisers, as well as matrix inversion made possible by floating-point arithmetic and IRC (interference rejection combining) receivers. The MSC8157 incorporates a high-speed DDR interface, ample internal memory, CPRI (common public radio interface) 6G antenna interfaces and two Serial-RapidIO Gen 2, enabling 5G per lane with sophisticated messaging capability.
The new DSPs include advanced WCDMA Chiprate acceleration, eliminating OEMs’ need to develop their own ASIC or FPGA. The high throughput and flexible Chiprate acceleration with capacity of up to 512 physical channels allows OEMs to deploy their own variant of Chiprate algorithms.
For more information contact Marian Ledgerwood, Future Electronics, +27 (0)21 421 8292, marian.ledgerwood@futureelectronics.com, www.futureelectronics.com
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| Email: | marian.ledgerwood@futureelectronics.com |
| www: | www.futureelectronics.com |
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