Altera announced the release of version 11.0 of it Quartus II software for CPLD, FPGA and HardCopy ASIC designs.
The new release features the production release of Altera’s next-generation system integration tool, Qsys. The new Qsys tool features an FPGA-optimised network-on-a-chip (NoC)-based interconnect delivering up to 2x higher interconnect performance compared to SOPC Builder. Qsys improves system scalability for large FPGA designs and enables support for industry standard interfaces (Avalon and AMBA AXI from ARM, etc).
Qsys uses a NoC-based interconnect to deliver higher-performance systems compared to conventional bus and switch fabric architectures. To demonstrate the capabilities of the high-performance interconnect in version 11.0, Altera offers a PCIe to DDR3 reference design built using Qsys. The reference design achieves throughput of over 1400 MBps between a memory-mapped PCIe Gen2 x4 Endpoint and an external DDR3 memory.
The design uses an automatically pipelined, NoC-based interconnect to packetise data for easier and faster transport. The reference design demonstrates how an Altera-provided PCIe IP core saves development time by eliminating the need to develop transaction layer packet (TLP) encoding/decoding logic and by simplifying PCIe protocol interface complexity. Customers can download the reference design from the Qsys page of Altera’s website at www.altera.com/qsys.
Qsys enables designers to develop large, scalable systems with a hierarchical design flow feature. Using hierarchy, designers can divide large FPGA designs that include a high number of IP cores or system components into smaller sub-systems. This hierarchical design flow allows designers to easily manage each sub-system while giving them the ability to add additional sub-systems to the design with minimal impact on system performance.
Qsys delivers flexibility by automatically handling the bridging between multiple interface standards. Designers leveraging Qsys can develop systems using Avalon-based, Qsys-compliant IP cores, and can add IP cores that use a different industry standard interface in the future without replacing the original IP cores. Qsys supports the open-standard Avalon interface with this release. Future releases of Qsys will support additional industry-standard interfaces, such as AMBA AXI from ARM.
Quartus II software version 11.0 provides faster board bring-up through enhancements to the software’s external memory interface toolkit and transceiver toolkit. New performance and monitoring capabilities in the external memory interface toolkit improve productivity by helping achieve maximum memory efficiency. The enhanced transceiver toolkit delivers an improved channel manager interface and an updated transceiver control panel, so designers can optimise their transceivers for improved signal integrity and bring their boards up faster.
For more information contact EBV Electrolink, +27 (0)21 402 1940, [email protected], www.ebv.com
| Tel: | +27 11 236 1900 |
| Email: | [email protected] |
| www: | www.ebv.com |
| Articles: | More information and articles about EBV Electrolink |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version