Model Technology and Actel have announced an OEM agreement to provide Actel customers with easy access to ModelSim, a leading language-neutral simulation tool. Actel will integrate ModelSim into Libero, the company's next-generation integrated design environment recently introduced, allowing customers to easily access the simulation tool when developing and designing FPGAs. The ModelSim Actel version is specifically targeted to Actel's devices, which combine the flexibility and time-to-market benefits of FPGAs with the single chip and lower power benefits of ASICs.
ModelSim features powerful interactive debug capabilities, regression test support and superior memory utilisation for simulating a broad range of designs. The ModelSim Actel version is a powerful simulation tool that offers source-level debug for VHDL, Verilog and mixed-language as well as behavioural, structural and back-annotated dynamic simulation.
"Actel is committed to offering its customers a comprehensive design environment that integrates best-in-class tools and, as a result, improves quality of results," said John East, President and CEO at Actel. "With the integration of ModelSim, Actel's Libero provides our customers with access to the leading HDL simulation solution for programmable devices and will enable FPGA designers to achieve their productivity and time-to-market requirements."
"With this announcement Mentor Graphics expands its HDL simulation reach to approximately 90% of the programmable market," said Dr Walden Rhines, Chairman and CEO of Mentor Graphics. "Actel's customers now have access to a powerful simulation tool for Verilog and VHDL design that produces fast, accurate simulation results that maximise the performance of their FPGA designs."
For further information contact Kobus van Rooyen, ASIC Design Services, (011) 315 8316, [email protected]
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