Microsemi has unveiled its new SmartFusion2 system-on-chip (SoC) field programmable gate array (FPGA) family. The next-generation devices are designed to address fundamental requirements for advanced security, high reliability and low power in critical industrial, defence, aviation, communications and medical applications.
SmartFusion2 integrates inherently reliable Flash-based FPGA fabric, a 166 MHz ARM Cortex-M3 processor, advanced security processing accelerators, DSP blocks, SRAM, eNVM and industry-required high-performance communication interfaces all on a single chip.
Recent attacks on industrial, defence, aviation, communications and medical systems have highlighted the need for security and anti-tamper safeguards within electronic systems. SmartFusion2 includes security capabilities that make it easy to protect classified and highly valuable designs against tampering, cloning, overbuilding, reverse engineering and counterfeiting with state-of-the-art design protection based on non-volatile Flash technology.
The platform provides highly advanced design and data security capabilities starting with a robust root-of-trust device with secure key storage capability using a physically unclonable function (PUF) key enrolment and regeneration capability.
SmartFusion2 also protects against differential power analysis (DPA) attacks using technology from the Cryptographic Research Incorporated (CRI) portfolio. Users may also leverage built-in cryptographic processing accelerators including advanced encryption standard (AES) AES-256, secure hash algorithm (SHA) SHA-256, 384-bit elliptical curve cryptographic (ECC) engine and a non-deterministic random bit generator (NRBG).
Microsemi’s programmable logic solutions are used extensively in defence and aviation applications due to their high reliability and immunity to single event upset (SEU) occurrences, which can cause binary bits to change state and corrupt data and cause hardware malfunction. The need for SEU protection is also extending into industrial and medical applications.
Smartfusion2 devices are designed to meet many industry standards including IEC 61508, DO254 and DO178B, and feature SEU immunity of zero failures in time (FIT). As an additional benefit, the Flash FPGA fabric does not require external configuration, which provides an added level of security since the SoC FPGA retains its configuration when powered off and enables device ‘instant-on’ performance.
SmartFusion2 protects all its SoC embedded SRAM memories from SEU errors. This is accomplished through the use of single error correction, double error detection (SECDED) protection on embedded memories such as the Cortex-M3 embedded scratch pad memory, Ethernet, CAN and USB buffers, and is optional on the DDR memory controllers.
SmartFusion2 SoC FPGAs claim to offer designers 100x lower standby power compared to equivalent SRAM-based FPGAs without sacrificing performance. The Flash*Freeze standby power mode can be initiated with a simple command. In this mode all registers and SRAM retain state, I/O state can be set, the microprocessor sub-system (MSS) can be operational while low-frequency clock and I/Os associated with MSS peripherals can be operational.
The device can enter and exit Flash*Freeze mode in approximately 100 microseconds. This is ideal for low duty cycle applications where short bursts of activity are required, such as defence radio where size, weight and power are critical.
Microsemi’s Flash-based SoC FPGA consumes just 10 mW of static power for a 50 K LUT (look-up table) device, including the processor and without sacrificing performance. With the Flash*Freeze standby mode, power drops to 1 mW.
SmartFusion2 devices are available with a range of density from 5 K LUT to 120 K LUT plus embedded memory and multiple accumulate blocks for digital signal processing (DSP). High-bandwidth interfaces include PCI Express (PCIe) with flexible 5 G SERDES along with high-speed double data rate DDR2/DDR3 memory controllers.
The device also includes a microprocessor sub-system (MSS) with a 166 MHz ARM Cortex-M3 processor, on-chip 64 KB eSRAM and 512 KB eNVM. The MSS is enhanced with an embedded trace macrocell (ETM), 8 KByte instruction cache, and peripherals including controller area network (CAN), Gigabit Ethernet and high-speed USB 2.0. Optional security accelerators can be used for data security applications.
System designers can leverage the newly released, easy-to-use Libero SoC software toolset for designing SmartFusion2 devices. Libero SoC integrates advanced synthesis, debug and DSP support from Synopsys, and simulation from Mentor Graphics with power analysis, timing analysis and pushbutton design flow.
Firmware development is fully integrated into Libero SoC with compile and debug available from GNU, IAR and Keil, and all device drivers and peripheral initialisation is auto generated based on System Builder selections. The ARM Cortex-M3 processor includes operating system support for embedded Linux from EmCraft Systems, FreeRTOS, SAFERTOS and uc/OS-III from Micrium.
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