Altera’s latest development software release - Quartus II version 14.1 - features expanded support for the company’s Arria 10 FPGAs and SoCs. It provides immediate support for the hardened floating point DSP blocks integrated in Arria 10, and gives users a choice between three unique DSP design entry flows and allows them to achieve up to 1,5 TFLOPS of DSP performance. The software also includes several optimisations that improve designer productivity by accelerating design time.
The software allows developers to tap the FPGAs’ integrated IEEE 754-compliant, floating-point DSP blocks to quickly design and deploy solutions that address a range of computationally intensive applications, in areas such as high-performance computing (HPC), radar and medical imaging. These design flows include OpenCL for software programmers, DSP Builder for model-based designers and hardware description language (HDL) flows for traditional FPGA designers.
Additional features in Quartus II Software v14.1 include:
An enhanced Design Space Explorer II (DSE II) tool for faster timing closure, which delivers real-time status and reporting data to users. The data can be used to do side-by-side comparisons of multiple compiles being generated simultaneously on compute farms.
An optimised, centralised IP catalogue and improved graphical user interface (GUI) help to store and easily find all custom IP in a single location.
Additional support for Altera’s new non-volatile MAX 10 FPGAs, which feature dual-configuration Flash, analog and embedded processing capabilities in a small-form-factor, low-cost, instant-on programmable logic device.
Enhancements to the JNEye serial link analysis tool further simplify board-level design and planning. This tool, along with Arria 10 silicon models, is able to simulate transmission line models and estimate insertion loss and cross talk parameters in Arria 10 designs.
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