Xilinx announced the 2015.3 release of System Generator for DSP, a high-level tool for designing high-performance DSP systems using Xilinx ‘All Programmable’ devices. With System Generator, algorithm developers can create production-quality DSP implementations within the familiar MATLAB and Simulink model-based design environment in a fraction of the time compared to traditional RTL.
The latest release delivers higher-level design abstractions and seven times greater design productivity for the development of wireless radio algorithms realised through a combination of a new blockset, faster simulation and compilation run times.
With this new release, higher-level design abstractions are enabled through HDL Coder interoperability with System Generator block hierarchies for use with Vivado Design Suite. This allows a flexible mixture of high-level and target-optimised code to create the best implementation results. This new flow provides reusable data path implementations that easily connect to system-on-chip (SoC) platforms containing JESD204 and CPRI interfaces and wireless radio IP like crest factor reduction.
The usability of the System Generator blockset for digital up- and down-converters (DUC/DDC) has been greatly simplified for wireless algorithm development. Enhancements to improve verification and compile runtime have been added to the new blocks, all of which are configured with seven or fewer parameters.
The digital FIR filter block tightly integrates with the Filter Design and Analysis tool from MathWorks to build area efficient filters, including fixed-fractional interpolation or decimation types. The sine wave and complex product blocks greatly simplify modulator design for frequency conversion at high sample rates. The requantise block enables quick manipulation of data types to maximise dynamic range at any point in the data path.
With the System Generator waveform viewer, developers can easily cross probe into the block across multiple clock domains. The new interactive cross probing accelerates design exploration and provides iterative design closure. With timing analysis cross probing, algorithm developers can quickly identify their critical paths and single out bottlenecks that may affect throughput and latency of their algorithms to make swift adjustments. Also new to this release are improvements to hardware-based co-simulation which improve verification run time by 45 times.
System Generator for DSP 2015.3 is available now with support for Xilinx 7 series, UltraScale devices as well as early access support for UltraScale+ FPGAs and MPSoCs.
For more information contact Erich Nast, Avnet South Africa, +27 (0)11 319 8600, [email protected], www.avnet.co.za
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