Microsemi has become the first field programmable gate array (FPGA) provider to offer a comprehensive software tool chain and intellectual property (IP) core for RISC-V designs. RISC-V is a new instruction set architecture (ISA) which is now a standard open architecture under the governance of the RISC-V Foundation.
Microsemi’s RV32IM RISC-V core is available for its IGLOO2 FPGAs, SmartFusion2 system-on-chip (SoC) FPGAs or RTG4 FPGAs, with an Eclipse-based SoftConsole integrated development environment (IDE) hosted on a Linux platform and the Libero SoC Design Suite providing full design support.
Developed in collaboration with SiFive, the RV32IM core enables customers to design with an open ISA, enabling complete portability and a more secure processor architecture governed by a permissive BSD licence. It is especially compelling for applications such as safety and security, as the register transfer level (RTL) source code is available for inspection. For example, customers can verify the security of the processor themselves, which is not possible with other processors, as they have closed architectures. In safety-critical applications, customers can run multiple RISC-V cores to ensure if one fails there is a redundant core to take over.
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