Actel has enhanced Libero, its next-generation integrated design environment for field-programmable gate array (FPGA) development and design. In the new release, Libero includes support for mixed-mode design entry input, giving designers the choice of mixing either high-level VHDL or Verilog HDL language blocks with schematic modules within a design. Mixed-mode support enables designers to describe complex functions in HDL and 'stitch' those blocks together using schematic diagrams. This new capability is especially valuable for designers integrating intellectual property (IP) into complex FPGAs where time-to-market and productivity requirements are stringent.
Older design methodologies require a designer to manually re-implement a design module if it was created in a format different from the format of the overall design, says Actel. The enhanced Libero tool suite allows integration of such modules, eliminating the need for re-implementation. This mixed-mode capability has become important as programmable logic design density increases and IP utilisation and design re-use become a necessity.
The Libero tool suite is available in three versions: Platinum, Gold and Silver. Actel's Libero Platinum is a complete tool suite solution with unlimited design capacity and customer support. Libero Gold is for users designing system-level devices of 50 000 gates or less, while Libero Silver offers tool support from entry to programming for Actel devices of 10 000 gates or less, including Actel's eX family and the ProASIC A500K050, and is offered at no charge to qualified designers for one year.
For further information contact Kobus van Rooyen, ASIC Design Services, (011) 315 8316, [email protected]
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