Developed by XJTAG, the free XJTAG DFT Assistant for the Mentor Xpedition Designer product increase the design for test (DFT) and debug capabilities of the schematic capture and PCB design environment.
Printed circuit boards (PCB) are increasingly densely populated and access to pins under many packages, such as ball grid arrays (BGA), is virtually impossible. JTAG was designed to solve the problem of access and so it is vitally important to get the JTAG chain right at the design stage. Failure to identify and fix design errors at an early stage can result in a board re-spin and a costly delay to a project. XJTAG DFT Assistant helps validate correct JTAG chain connectivity, through full integration with the Xpedition schematic capture environment.
The XJTAG DFT Assistant comprises two key elements: the XJTAG Chain Checker and the XJTAG Access Viewer. The chain checker identifies common errors in a JTAG scan chain, such as incorrectly connected test access ports (TAP), where a single connection error would inhibit an entire scan chain from working. XJTAG Chain Checker identifies connection errors and reports them to the developer during the design process. Incorrectly terminated TAPs are also identified.
XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage could be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets that don’t have any JTAG access on the schematic.
While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from the Xpedition schematic capture environment to the XJTAG development software, where additional tests can be developed. These can then be used to test real hardware, as soon as it’s available.
This software is free for Xpedition users of VX.2.1 or higher and can be downloaded from www.xjtag.com/Xpedition.
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