Programmable Logic


Million gate flash FPGA breaks density barrier

27 March 2002 Programmable Logic

Based on a 0,22 µm process, Actel's new single-chip, in-system programmable ProASICPLUS FPGA family will consist of six devices ranging in density from 150 000 to 1-million system gates. The devices are nonvolatile, live at power up, highly secure and require no separate configuration memory. Additional new features include multiple phase-locked loops (PLLs), support for up to 198 Kb of two-port embedded SRAM and 712 user-configurable I/Os, and improved in-system programmability.

Barry Marsh, vice president, product marketing at Actel says, "A huge market opportunity exists for Actel to directly address those FPGA and ASIC designers looking for the density range, flexibility and nonvolatility they require. Additionally, the ProASICPLUS family's new features, paired with a design security advantage, positions Actel to aggressively penetrate these target markets."

ProASICPLUS devices deliver high performance with system speeds of up to 100 MHz and allow designers to interface between 3,3 and 2,5 V devices in a mixed-voltage environment. The family contains two advanced clock-conditioning blocks, each consisting of a PLL core, delay lines and clock multiplier/dividers. Additionally, two high-speed LVPECL differential input pairs accommodate clock or data inputs. In-system programmability is supported through the IEEE standard 1149.1 JTAG interface.

The ProASICPLUS family is supported by Actel's Designer software, which includes place-and-route, timing analysis and memory generation functionality. Targeting both ASIC and FPGA environments, the devices are also supported by third-party design tools. According to Actel, because the ProASICPLUS devices work equally well with ASIC and FPGA design methodologies, designers can create high-density systems using existing tools and flows.

Advantages

The ProASICPLUS devices offer levels of design security beyond SRAM-based FPGAs and conventional ASIC solutions. These FPGAs are user-programmed with a multi-bit key that blocks external attempts to read or alter the configuration settings.

The first members of the ProASICPLUS family, the APA750 and APA1000, offer 750K and 1-million system gates, respectively. A portable programmer and complete demonstration platform are also available.

For further information, contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, [email protected]



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