As transmission speeds increase (10 gigabit SERDES, gigabit Ethernet, etc) there is greater need for high-speed serial transmission methods - usually Differential Signals (DS) for many companies. However, one must be aware that it has design restrictions that must be adhered to for successful design.
Here we look at the main requirements for DS, ie overcoming differential unbalance, controlling crosstalk, and providing the correct PCB layout.
Differential unbalance
The ideal DS transmission is seen in Figure 1. If the two pathways are the same electrical length (EL), the return currents cancel. What would happen if they are not the same EL? The unbalance fraction is defined in Figure 1. When one edge arrives before the other, the return currents will not cancel until the second edge arrives. During this time, two detrimental effects will occur, a reflection on the line of the first arriving signal and crosstalk between the lines. Therefore, the layout personnel must be cognisant of these scenarios:
1. Propagation delay - (about 140 ps/in. outer layer, 180 ps/in. inner layer)
2. Vias - Each time a trace is disrupted by a via, the inductance of the total path is increased, thereby changing the EL.
3. Keep always - If one trace has to deviate around a pin, via, anti-pad, etc, the EL will be affected.
Crosstalk
Figure 2 defines an example of noise (crosstalk) coupling into a differential pair. Now, if the noise is only coupled to one and not the other, the receiver output data is useless.
Differential signals use two lines driven with complementary waveforms. A virtue of differential signals is that most noise sources couple roughly the same noise onto both lines. The differential receiver is designed to ignore signal components that are common to both lines (the common mode) while responding to the difference between the two lines (the differential mode), rejecting the coupled noise. A related benefit of differential signals is that the electromagnetic interference (EMI) generated by each line in the differential pair is largely cancelled by the other line.
PCB layout
There are three methods for laying out differential pairs: asymmetric; dual (broadside); side-by-side (edge).
Dual is very hard to accomplish due to accuracy of lamination process (x, y, and O errors among layers). The tradeoffs between dual and edge are:
* Side-by-side routing distances dual-distance and via length's electrical length.
* Three layer versus two layer lamination accuracy.
* Etching on 2 Cu planes versus 1 Cu plane.
Most companies will design using on-the-edge layout with the two sheets of Cu being ground planes. A major key to successful DS is careful planning of layout for EL and signals that are protected by the ground layers.
Robert Hanson will be delivering high-speed digital design seminars in South Africa during June. Contact [email protected], for further details.
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