Industry's first monolithic desynchronisation solution - 8 May 2002 - ASIC Design Services

Industry's first monolithic desynchronisation solution
8 May 2002, Telecoms, Datacoms, Wireless, IoT

Exar offers an integrated monolithic solution to address desynchronisation requirements when mapping/demapping from SONET/SDH (synchronous) to DS3/E3 (asynchronous) environments. This unique desynchronisation solution will be embedded in Exar's physical interface (LIU) and data aggregation devices. The first data aggregation device utilising this capability was the company's OC-12 mapper (XRT94L43) announced last October. This new LIU is a single-channel DS3/E3/STS-1 device offered in two modes: one with desynchronisation (XRT75L00D), and the other with jitter attenuation only (XRT75L00). The devices use an innovative combination of analog and digital signal processing technologies to achieve their results. Applications include access equipment, digital cross-connect systems, routers, and digital subscriber line access multiplexer (DSLAMs).

Why does the clock need desynchronisation?

The process of mapping and subsequent de-mapping of individual DS3 or E3 signals into SONET's Synchronous Payload Envelope (SPE) introduces excessive jitter and timing irregularities. Examples of jitter sources include mapping jitter, caused by bit justification, or stuffing, to match the asynchronous bit rate to a synchronous transport signal; and pointer jitter, the outcome of frequency mismatches between two networks that offset the payload and cause pointer movement.

Discrete desynchronising solutions use a combination of a very narrow-bandwidth crystal oscillator based phase locked loop (PLL) referred to as a voltage control oscillator (VCXO), and a deep FIFO for each data rate and channel. In multi-channel and multi-rate applications, external VCXOs are multiplied by the number of supported rates and channels. Exar's solution uses only one highly integrated programmable PLL so each channel can support multirate (DS3, E3 or STS-1) operations.

Here jitter/timing irregularities are removed, and then desynchronised to provide a smooth GR-253-CORE specification-compliant clock signal. Once this operation is complete the signal is suitable for retransmission and returned to the data stream.

The XRT75L00 and XRT75L00D incorporate an independent receiver, transmitter and jitter attenuator in a single 52-pin TQFP package.

For further information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, kobus@asic.co.za