Solution for synchronising multiple direct digital synthesizers
22 May 2002
DSP, Micros & Memory
The fast frequency hopping, extreme tuning resolution, and programmable phase control attributes of direct digital synthesizers (DDSs) make them a compelling choice for a wide variety of signal synthesis applications. However, many applications, such as phased-array radar and critical timing generators, require precise phase-synchronisation of multiple synthesized output signals. Phase synchronisation of multiple synthesizers is a challenge for PLL and other traditional analog-based architectures.
The AD9852/9854 and AD9850/9851 DDS devices from Analog Devices, with up to 14 bits of programmable phase-offset resolution (for AD9852/9854), provide an easy and precise solution for phase synchronisation of multiple synthesized signals. The synchronisation of multiple DDS devices is accomplished as follows.
There are two basic timing requirements to be met in order for successful synchronisation to occur. The first, and somewhat obvious, is a coincidental REF clock between all DDSs. Coincidental means that the REF clock pins of each DDS have REF clock timing coincident in time (Figure 1). This is accomplished through proper PCB layout.
Figure 1. PCB layout must ensure that REFCLK edge arrives coincidentally at clock input pins of multiple DDSs
The second timing requirement between all DDS devices is the coincidental transfer of the programmed input data to the DDS core. Performing this transfer are two key signals: FQ_UD for the AD9850/9851 and I/O update clock for the AD9854/9852. If the rising edges of these two signals are sent synchronously to the multiple DDSs, along with proper set-up time relative to the REF clock, then synchronisation will be achieved (Figure 2).
Figure 2. Dual AD9851 set-up for quadrature output
With proper procedure, synchronisation can be readily achieved among multiple DDSs; Figure 3 illustrates synchronisation of two AD9851 devices. In this case, the REFCLK frequency is set to 10 MSa/s. Synchronisation is also achievable up to the maximum system clock rate (including PLL mode).
Figure 3. DDS synchronisation (conditions: VCC = 5 V, REFCLK = 10 MSP, nonPLL mode, 25°C)
Typical applications are for clock synthesis, ADC encode generators, and agile local oscillators.
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