The TigerSHARC DSP from Analog Devices targets infrastructure equipment with a new level of integration and the unique ability to process 8-, 16- and 32-bit fixed-point and floating-point data types on a single chip. Each of these data types is critical to the next generation of telecommunications protocols currently under development, including IMT-2000 (also known as 3G wireless) and XDSL (Digital Subscriber Line).
In one chip, ADI has integrated six megabits of SRAM, fixed- and floating-point data type support, four bi-directional link ports, a 64-bit external port, 14 DMA (Direct Memory Access) channels and 128 general purpose registers. For large scale applications that require clusters of DSPs, ADI has integrated its patented link port technology enabling direct chip-to-chip connections without the need for complex external circuitry.
Static superscalar architecture
The TigerSHARC DSP architecture blends best practices in microprocessor design to enable the highest performance programmable DSP for realtime systems. Using a static superscalar architecture it incorporates many aspects of conventional superscalar processors, including a load/store architecture, branch prediction, and a large, interlocked register file. Up to four instructions can he executed in parallel in each cycle. The term 'static superscalar' is applied because instruction level parallelism is determined prior to run-time and encoded in the program. All the registers are interlocked, supporting a simple programming model that is independent of the implementation latencies and is fully-interruptible. Branch prediction is supported via a 128-bit entry Branch Target Buffer (BTB) that reduces branch latency.
Eight MACs/cycle
There are two computation blocks (Processing Elements X and Y) in the TigerSHARC DSP architecture, each containing a multiplier, ALU, and 64-bit shifter. With the resources in these blocks, it is possible to execute eight 40-bit MACs on 16-bit data, two 40-bit MACs on 16-bit complex data, or two 80-bit MACs on 32-bit data, in a single cycle. With 8-bit data types, the architecture executes 16 operations per cycle.
TigerSHARC DSP is a register-based load/store architecture, where each computation block has access to a fully orthogonal 32-word register file.
Memory architecture
The TigerSHARC DSP features a short vector memory architecture organised internally in three 128-bit wide banks. Quad (four words, 32 bits each), long (two words, 32 bits each), and normal word accesses move data from the memory banks to the register files for operations. In a given cycle, four 32-bit instruction words can he fetched, and 256 bits of data can be loaded to the register files or stored into memory. Data in 8-, 16-, and 32-bit words can he stored in contiguous, packed memory. Internal and external memories are organised in a unified memory map. The partition between program memory and data memory is user-determined. The internal memory bandwidth for data and instructions is 8,64 GB/s.
Instruction set
The instruction set directly supports all DSP, image, and video processing arithmetic types including signed, unsigned, fractional, and integer data types. There is optional saturation (clipping) arithmetic for all cases. Contact the distributor for a table that shows a subset of the compute block and load/store instructions.
Development tools
TheVisualDSP IDE (integrated development environment) provides the interface to a complete suite of tools, including optimising C compiler, assembler, linker, cycle-accurate simulator, and debugger. White Mountain DSP emulators provide easier and more cost-effective methods for engineers to develop and optimise DSP systems, shortening product development cycles for faster time-to-market.
The TigerSHARC DSP platform offers designers a flexible development environment that supports both C and assembly programming. It features robust and efficient C compiler tools, achieving up to 70% compiler efficiency. For time-critical inner loops, DSP programmers can turn to the machine's assembly language to produce the highest performance code. This platform, despite its sophisticated architecture, is practical to program in assembly, with features such as easy-to-learn algebraic assembly language syntax, predictable 2-cycle delay for all computations, 128 fully-interlocked, general purpose registers, and branch prediction.
For further information contact Analog Data Products SA on 011 531 1400.
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