Actel has significantly enhanced its Designer field-programmable gate array (FPGA) software solution. The new release features two new capabilities - SmartPower, a robust power analysis tool, and Netlist Viewer, a utility that allows designers to display the netlist in a hierarchical manner. These enhancements enable customers to create designs for Actel's next-generation FPGA devices in less time. Additionally, says Actel, the performance of the timing analysis and layout utilities has increased substantially - up to 50% faster on specific customer designs.
The power analysis tool, SmartPower, enables quick identification of power consumption problems within a component and then optimises accordingly. This feature offers a distinct advantage over competitive power analysis tools that estimate the power consumption of overall designs rather than components. SmartPower also enables detailed hierarchical reports of the dynamic power consumption of a design. This includes design level power summary, average switching activities, ambient and junction temperature readings.
The addition of Netlist Viewer allows users to display the netlist in a hierarchical manner, trace signals and explore each level of the design. This assists in meeting area and timing goals and aids in critical path identification. Actel Designer supports established electronic design automation (EDA) standards, such as Verilog/VHDL/EDIF netlist formats. The new Netlist Viewer enables designers to view a graphical representation of the netlist, display the netlist in a hierarchical manner or search for instances, nets and ports.
For more information: Kobus van Rooyen, ASIC Design Services, 011 315 8316, kobus@asic.co.za
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