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80C51 linear address range expanded to 16 MB
14 August 2002, DSP, Micros & Memory

Philips Semiconductors' 87C51Mx2 microcontroller family breaks the 64 KB barrier. This 8 bit 80C51 supports up to 16 MB of on-chip linear addressable memory. As a leading supplier of 80C51 solutions, the company extends the 80C51 architecture into advanced and emerging applications in the communications and consumer markets.

The 87C51Mx2 microcontroller family is based on the company's 51MX core. The 51MX (Memory eXtension) combines a significant increase in on-chip program and data memory together with high-level C language performance enhancements. Full binary object code compatibility is maintained, allowing design engineers to re-use existing 80C51 program code. The architecture also retains 80C51 bus compatibility to allow re-use of existing peripherals and ASICs.

The 51MX is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. Its 23 bit linear address supports up to 16 MB of on-chip or offchip program and data memory. The 87C51MC2 is available with 96 KB of OTP (one-time programmable) memory and 3 KB of RAM. Devices operate with supply voltages from 2,7 to 5,5 V and run at up to 24 MHz (5 V, six clock cycles per machine cycle) with a typical instruction cycle time of 250 ns. Includes an integrated PCA (programmable counter array), five capture/compare modules, two full-duplex enhanced UARTS, an industry-standard serial peripheral interface (6 Mbps) and a configurable watchdog timer.

For more information: Mutronics (Value Added Distributor), 011 608 1460, mut@iafrica.com


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Further reading:

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