mobile | classic
Dataweek Electronics & Communications Technology Magazine

Follow us on:
Follow us on Facebook Share via Twitter Share via LinkedIn


Electronics Buyers' Guide

Electronics Manufacturing & Production Handbook 2019


Evaluation platform for ProASICPLUS FPGAs
10 September 2002, Programmable Logic

Actel offers a low-cost evaluation board for the company's flash-based ProASICPLUS field-programmable gate arrays (FPGAs). The new evaluation board, developed in conjunction with First Silicon Solutions (FS2), allows designers to access the in-system programmability (ISP) feature of Actel's nonvolatile ProASICPLUS devices as well as to explore various chip characteristics, such as I/O drive characteristics, boundary scan operation, embedded RAM block performance and phase-locked loop (PLL) operation. With this platform, designers can quickly and accurately evaluate their own designs to determine suitability for their application-specific integrated circuit (ASIC) alternative applications in the industrial, communications, networking and avionics markets.

"Since its launch in January 2002, we have seen unprecedented success with our ProASICPLUS offerings due to its single-chip, ASIC-like architecture; the inherent security benefits of Actel's flash-based FPGAs; and the ISP capability that enables reprogramming of the devices in the field," said Bryon Moyer, senior director of tools and technical marketing at Actel. "The Actel Libero integrated design environment and Actel Designer software combined with the portable Flash Pro programmer and the new low-cost evaluation board developed with FS2 provide our customers complete support when using Actel's ProASICPLUS family of FPGAs in their communications, industrial and avionics designs."

"We were happy to work closely with Actel to develop the new low-cost evaluation board for ProASICPLUS FPGAs," said Rick Leatherman, president of First Silicon Solutions. "When used with the Flash Pro programmer, customers have an easy way to evaluate Actel's flash-based FPGA technology."

To enable the user to evaluate any ProASICPLUS device, Actel offers a BG456 prototyping socket as part of the evaluation board. Other features include a Zilog eZ80 microcontroller, 2 MB flash RAM, 2 MB SRAM, and an integrated UART. Prototyping headers enable the user to add external components when creating a system that is similar to the user's final product. A standard programming header is also included, allowing the user to program the ProASICPLUS device with either the Flash Pro or Silicon Sculptor programmer from Actel.

For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316,

Supplied By: ASIC Design Services
Tel: +27 11 315 8316
Fax: +27 11 315 1711
  Share on Facebook Share via Twitter Share via LinkedIn    

Further reading:

  • Radiation-tolerant PolarFire FPGA
    23 October 2019, Avnet South Africa, Programmable Logic
    Developers of spacecraft electronics use radiation-tolerant (RT) field programmable gate arrays (FPGAs) to create on-board systems that meet the demanding performance needs of future space missions, survive ...
  • FPGA video and image processing ecosystem
    26 June 2019, Altron Arrow, Programmable Logic
    Microchip Technology, via its Microsemi subsidiary, announced its Smart Embedded Vision initiative that provides solutions for designing intelligent machine vision systems with Microchip’s low-power PolarFire ...
  • RISC-V based FPGA architecture
    30 January 2019, Altron Arrow, Programmable Logic
    Microchip, via its Microsemi Corporation subsidiary, announced an extension to its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs at the RISC-V Summit during December 2018. ...
  • RFSoC architecture by Xilinx
    14 November 2018, Avnet South Africa, Telecoms, Datacoms, Wireless, IoT, Programmable Logic
    Xilinx rolled out its Zynq UltraScale+ RFSoC family, an architecture integrating the RF signal chain into a system-on-chip (SoC) for high-performance RF applications. Based on the 16 nm UltraScale+ ...
  • RISC-V based FPGA architecture
    14 November 2018, Altron Arrow, Programmable Logic
    Microchip, via its Microsemi Corporation subsidiary, announced an extension to its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs at the RISC-V Summit during December 2018. ...
  • Thermal design incorporating EDA and MDA design flows
    13 June 2018, ASIC Design Services, Design Automation
    Electronics cooling design and simulation applications have to be quick, reliable and integrated into a fast-moving, complex design process.
  • DFT assistant for Mentor Xpedition
    13 June 2018, ASIC Design Services, Test & Measurement
    Developed by XJTAG, the free XJTAG DFT Assistant for the Mentor Xpedition Designer product increase the design for test (DFT) and debug capabilities of the schematic capture and PCB design environment. ...
  • Embedded deep learning framework for FPGAs
    18 April 2018, ASIC Design Services, This Week's Editor's Pick, Programmable Logic
    ASIC Design Services has developed a scalable and flexible embedded deep learning solution that allows for the implementation of a wide range of convolutional neural networks on FPGAs.
  • PolarFire FPGAs from Microsemi
    15 November 2017, ASIC Design Services, Electronics Technology
    Microsemi unveiled the cost-optimised PolarFire field programmable gate array (FPGA) product family, delivering what the firm claimed as the industry’s lowest power at mid-range densities with 12,7 ...
  • XJTAG updates boundary scan software
    11 October 2017, ASIC Design Services, Test & Measurement, Design Automation
    XJTAG has launched a major update to its flagship software, XJDeveloper. XJTAG’s unified test and programming IDE, XJDeveloper, is a development and debug environment that makes it quick and easy to set ...
  • IDE supporting RISC-V instruction set architecture
    19 July 2017, ASIC Design Services, Design Automation
    Microsemi announced the release of its SoftConsole version 5.1, the world’s first available Windows-hosted Eclipse integrated development environment (IDE) for designs utilising RISC-V open instruction ...
  • Electronic Product Creation Seminars
    19 July 2017, ASIC Design Services, News
    Electronic Product Creation Seminars    14 August 2017 – Stellenbosch    16 August 2017 - Durban    17 August 2017 – Midrand ASIC Design Services, in conjunction with Mentor, a Siemens Business, XJTAG and ...

Technews Publishing (Pty) Ltd
1st Floor, Stabilitas House
265 Kent Ave, Randburg, 2194
South Africa
Publications by Technews
Dataweek Electronics & Communications Technology
Electronics Buyers’ Guide (EBG)

Hi-Tech Security Solutions
Hi-Tech Security Business Directory

Motion Control in Southern Africa
Motion Control Buyers’ Guide (MCBG)

South African Instrumentation & Control
South African Instrumentation & Control Buyers’ Guide (IBG)
Terms & conditions of use, including privacy policy
PAIA Manual


    Classic | Mobile

Copyright © Technews Publishing (Pty) Ltd. All rights reserved.