Signal processing units and system-on-chip (SoC) units usually possess abruptly changing load transient profiles. This load transient will result in a disturbance on the supply voltage that is critical in radio frequency (RF) applications, as the clock frequency will be highly affected by the varying supply voltage. As a result, RFSoCs usually apply blanking time during the load transient. In 5G applications, information quality is highly related to this blanking period during the transition. Thus, there is an increasing need to minimise the load transient effect on the power supply side to improve the system-level performance for any RFSoC system. This article will introduce several methods used in RF applications to achieve fast transient response in a power supply design.
Fast transient silent switcher 3 family for RF applications
One of the most straightforward methods to achieve fast transient power rails is to select regulators that feature fast transient performance. The Silent Switcher 3 family of ICs features exceptionally low-frequency output noise, fast transient response, low EMI emissions, and high efficiency. It features an ultra-high-performance error amplifier design that can provide extra stabilisation even with an aggressive compensation. The 4 MHz maximum switching frequency enables the IC to push the control loop bandwidth to the mid-hundred kHz range in a fixed frequency peak current control mode.
Figure 1 shows a typical 1 V output power supply based on the LT8625SP for the 5G RFSoC, which needs fast transient response and low ripple/noise level at the same time. The 1 V load consists of both transmitted/received related circuits as well as local oscillators (LOs) and voltage-controlled oscillators (VCOs). The transmitted/received loads see abrupt load current change in the frequency division duplex (FDD) operation. At the same time, LOs/VCOs see constant load but require critical high accuracy and low noise. The high bandwidth feature of LT8625SP enables designers to power the two critical 1 V load groups from a single IC by separating the dynamic load and static load with a second inductor (L2). This circuit can be modified to accommodate other output combinations, like 0,8 V and 1,8 V, that can all directly supply the RFSoC load without the LDO regulator stage due to the ultralow noise in the low frequency range, low voltage ripple, and ultrafast transient response.
In time division duplex (TDD) mode, the noise critical LOs/VCOs become loaded and unloaded together with the transmit/receive mode changes. Thus, a simplified circuit as shown in Figure 3 can be used as all the loads are considered to be dynamic load while a more critical postfiltering is required to maintain the low ripple/low noise feature for the LOs/VCOs. A three-terminal capacitor in feedthrough mode can be used to achieve enough postfiltering with a minimised equivalent L that maintains a fast bandwidth for the load transients. The feedthrough capacitor together with the remote side output capacitors forms two more LC filter stages while all the Ls come from ESLs of the three-terminal capacitor, which is very small and less harmful to the load transient. Figure 3 also illustrates an easy remote sensing connection for the Silent Switcher 3 family. Due to the unique reference generation and feedback technology, one only needs to Kelvin connect the SET pin capacitor’s (C1) ground and the OUTS pin to the desired remote feedback point. No level shifting circuits are needed for this connection.
Precharge signals drive silent switcher 3 family for fast transient response
In some cases, the signal processing unit is powerful with enough GPIOs, and the signal processing is well scheduled as the transient event can be known ahead of time. This usually happens in some FPGA power supply designs where the precharge signal can be generated to help power the supply transient response. Figure 3 shows a typical application circuit using the precharge signal generated by the FPGA to provide a bias before the real load transition happens so that the LT8625SP can have extra time to accommodate the load disturbance without too large a VOUT deviation and recovery time. The tuning circuit from FPGA’s GPIO to the input of the inverter has been omitted as the precharge signal is acting as a disturbance on the feedback. The level is controlled to be 35 mV. Moreover, to avoid the precharge signal effect on the steady state, a high-pass filter is implemented between the precharge signal and the OUTS.
Active drooping on circuit for ultrafast recovery transient
In beamformer applications, the supply voltage changes all the time to accommodate different power levels. As a result, the accuracy requirement for the supply voltage is usually 5 to 10%. In this application, stability is more important than the voltage accuracy as a minimised recovery time during the load transient will maximise the data processing efficiency. A drooping circuit perfectly fits into this application as the drooping voltage will reduce or even eliminate the recovery time. Figure 4 shows the schematic for an active drooping circuit for the LT8627SP. An extra drooping resistor has been added between the error amplifier’s negative input (OUTS) and the output (VC) to maintain a steady state error in the feedback control loop during the transient. The drooping voltage can be expressed as:
Whereas ∆VOUT is the initial voltage variation caused by the load transient, ∆IOUT is the load transient current, and g is the VC pin to switch current gain. In designing the drooping circuit shown in Figure 4, special considerations need to be taken:
• The drooping current should not exceed the VC pin current limit. For LT8627SP’s error amplifier output, it is proper to limit the current to below 200 µA to avoid saturation and this can be achieved by changing R7 and R8 values.
• The drooping voltage needs to accommodate the output capacitance so that the voltage deviation during the transient is on a similar level of the drooping voltage to achieve minimum recovery time during the transient.
Conclusion
The wireless RF field is becoming increasingly calculation dependent and sensitive to the transient response time due to the time-critical nature of the high-speed signal processing. System design engineers face challenges to increase the power supply transient response speed so that the blanking time can be minimised. The Silent Switcher 3 family is the next-generation of monolithic regulators optimised for noise sensitive, intensive dynamic load transient solutions in wireless, industrial, defence, and healthcare fields. Based on the load conditions, special techniques and circuits can be applied to further improve the transient response.
| Tel: | +27 11 923 9600 |
| Email: | [email protected] |
| www: | www.altronarrow.com |
| Articles: | More information and articles about Altron Arrow |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version