Using AMD HLS to supercharge your design performance
30 April 2024
DSP, Micros & Memory
This free workshop, delivered in two half-day sessions, explores the power and capabilities of High-Level Synthesis (AMD Vitis HLS) to dramatically accelerate embedded software to hardware speeds. The workshop will benefit anyone looking for a thorough introduction to high-level synthesis using the AM Vitis Unified IDE.
It will provide an overview of the HLS design process, explain the component development flow, demonstrate how to explore design alternatives using directives, and provide an introduction to interfacing the accelerated hardware block. Further details will be provided to optimise performance by optimising dataflows and pipelining.
The workshop is designed to maximise individual engagement and learning. Attendees are encouraged to actively participate in the learning process. There are no specific hardware requirements for this training.
Date: 23-24 May 2024
Start time: 9:30 SAST
Further reading:
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