Preservation of intellectual property (IP) in the field of electronics has become a difficult task, as most products can be duplicated easily through reverse engineering.
This has created a pressing demand to enhance security measures to safeguard the core IP of electronics. A team of applied engineers from Rice University is researching a technology that might provide a degree of remedy.
The engineers have demonstrated a novel flexible design to fabricate microchips with an attribute that enables a single integrated circuit (IC) to support multiple versions of a design. The design was demonstrated at the Design Automation Conference (DAC) in California during June. The microchips that are fabricated in this way are known as N-variant ICs and they purportedly provide much better security for the core IP when compared to the traditional IC chips
This is made possible through the microchip's ability to presume either a single identity or multiple identities in the form of subsets. This property of the chip is due to the exclusivity of the IC's variant, which switches between the versions by choosing different components of the data path and control circuitry. The swaps between the variants can be triggered externally or through automated self-adaptive internal triggers.
Some of the advantages of this technology include ease of installation and low cost of operation. The technology can be readily incorporated into the existing synthesis flow without making any drastic changes to the system, except for the integration of the new algorithm for the system to follow. The overhead cost is also not too high, as the methodology permits a single mask to yield many different ICs. As the mask cost in state-of-the-art silicon technology is prohibitive, the only way to be economically viable is to produce many chips from one mask.
The other prominent benefit obtained is that the approach implicitly enables the strategic reconfigurability of application-specific integrated circuits (ASICs) without compromising on the pre-existing benefits such as low power, speed and area metrics.
The virtues and exclusivity of the technology enable it to span a wide array of applications. This technology comes in handy in domains such as fabrication of secure portable embedded devices, thermal management, and post-silicon optimisation.
To further enhance the technique, the engineers have proposed other algorithms that may incur even lower overheads, although these algorithms are yet to be programmed and tested. They are also looking into industrial collaborations to speed up the process of commercialising this technique.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)21 680 3274, [email protected], www.frost.com
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