Over the last decade, computers have been evolving at an unprecedented pace, with a new generation of processor and memory device being released every 12 to 18 months. This has been in line with the prediction of Moore’s Law that transistor densities will double every 18 months. However, researchers fear that we are fast approaching the theoretical limits of transistor miniaturisation.
With every increase in chip density, transistors are packed closer together and more power passes through the IC. There are however a number of problems associated with packing the transistors at such high densities. Two of the most critical are thermal build-up and data instability.
As a typical central processing unit (CPU) or graphics processing unit (GPU) requires a significant amount of power, developments of hot-spots are common. Even with elaborate cooling solutions, the situation could still lead to thermal runaway.
The issue of data stability is even more important in light of the fact that we are very close to the theoretical limit of transistor density. If we move to even smaller transistors and pack them any closer, their switching states could be affected by neighbouring transistors. This could lead to data corruption at the binary level and the data could be irrecoverable.
Conventional memory chips in electronic devices are made up of transistors, resistors and capacitors built in layers on a silicon wafer through a photolithographic process, during which precise patterns are etched on the silicon to form the chip. Today’s technology allows several million transistors to be built on a piece of silicon, which is the size of a pinhead. However, even such high densities will not be sufficient for tomorrow’s computing needs. This has led many researchers to look for alternate solutions. One of the more promising solutions currently being pursued is a nano-electromechanical (NEM) switched capacitor approach.
While volatile random access memory (RAM) remains one of the most commonly used memory components, it does have a number of limitations besides the scalability limit. Both SRAM and DRAM require complex feature architecture and, due to factors such as current leakage, need to be refreshed.
Researchers have been experimenting for a while now on electromechanically driven switches to replace silicon-based transistors. However, getting the devices down to the required scale has been a significant hurdle.
Electromechanically driven switches contain moving parts and possess excellent on-off ratios and fast switching characteristics, thus making them well suited to high-performance computing, notwithstanding the size constraint. Another advantage with such devices is the physical separation between the switch and the capacitor. This means that the data leakage problem is significantly reduced. However, until now the technology has not been a viable alternative to silicon-based arrangements because it involved larger cells and more complex fabrication processes.
Prof. Gehan Amaratunga, head of the EPEC group within the electrical engineering division of the Cambridge University and his fellow researchers appear to have a solution. They have succeeded in developing a novel NEM switched capacitor based on vertically aligned multiwalled carbon nanotubes (CNTs).
Rather than creating memory chips through a photolithographic process, nanotubes are grown in place on a silicon wafer by allowing a carbon-carrying gas to absorb onto a hot nickel surface, which acts as a catalyst for the nanotube growth. The length of time for which the nanotube is grown determines its length, which in turn determines its mechanical properties such as stiffness and resonant frequency. The resonant frequency of the nanotube structure determines the maximum switching speed of the NEM switch and its stiffness determines how much charge is needed to deflect it into contact with the other element of the cell.
The device operation is quite simple. Essentially, one nanotube (which stores a charge) bends toward a neighbouring static nanotube. Upon touching, the circuit is completed and current flows through to a capacitor structure formed around the static nanotube. This charge is used to represent a bit of information; a charged capacitor represents an on state and an uncharged capacitor represents an off state.
The vertical nature of the NEM capacitor structure allows for high-integration densities, reducing both process costs and size requirements. There is a sharp transition between the on and the off state of the switch, which means that a very small difference in voltage can change the state of the device, reducing the amount of power required for its operation.
Though similar approaches have been attempted in the past, Frost & Sullivan believes this is the first time researchers have managed to control the number and spatial location of nanotubes over large areas with the precision needed for the production of integrated circuits.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)21 680 3274, patrick.cairns@frost.com, www.frost.com
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