Single-electron devices are nanoscale devices that can control the movement of individual electrons. These devices are likely to emerge as a resolution to the industrial demand for the drastic shrinkage of electronic devices, as they hold promise for ultra-high density packaging of electronic components.
Besides miniaturisation, the substitution of conventional electronic devices with single-electron electronic devices provides benefits such as extremely low power consumption and high operational speeds. However, the existing single-electron device fabrication methodologies incur very high costs due to the use of sophisticated technologies for nanoscale pattern definition, such as e-beam lithography, nano-oxidation using scanning tunnelling microscopy (STM)/atomic force microscopy (AFM), mechanically controlled break junctions and electromigration.
The high cost involved and the complexity of the procedures do not favour large-scale production. For over a decade, researchers from around the globe have therefore been striving to devise a cost-effective method to fabricate these devices.
A research team headed by Assistant Professor Seong Jin Koh from the University of Texas at Arlington has now unveiled an innovative technique to fabricate single-electron devices. The invention is said to have overcome the currently existing barriers that have held back the devices’ widespread adoption in a variety of applications.
The team’s approach for constructing the devices involves the use of conventional integrated circuit fabrication equipment and processes, which include photolithography, thin-film deposition and etching. The resultant structure is a complementary metal oxide semiconductor (CMOS) device that incorporates a stack of two electrodes – source and drain – that are separated by a thin layer of dielectric material. Gold nanoparticles are attached to the exposed surface of the stack using self-assembly of monolayers.
This approach is far less expensive when compared to the traditionally employed technologies. It also purportedly enables the parallel assembly of multiple devices simultaneously. In addition to these advantages, the newly constructed device is functional at room temperature. This sets it apart from those that are assembled using traditional methods, as most of the devices that were developed in the past needed to be cooled down to minus 250°C, making them impractical for widespread use.
The single-electron devices are expected to have several potential applications, some of which include the development of highly miniaturised portable memories with very large storage capacity, and highly sensitive measurement instruments to study fundamental problems in physics that are as yet unresolved. Apart from these, they are also expected to be of use in several commercial electronics and aerospace and defence applications.
Having validated the feasibility of the parallel fabrication of these nanoscale devices, the team’s current interest is centred on assembling an integrated system of single-electron transistors. The approach will be similar to that which was employed for the construction of the CMOS system. The team also intends to develop single-electron memories and then logic systems.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)21 680 3274, [email protected], www.frost.com
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