Development in single event transient detection technology

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13 May 2009 News News Circuit & System Protection

Information from Frost & Sullivan Technical Insights

Progress in complementary metal oxide semiconductor (CMOS) technology has led to smaller dimensions of the devices, increased transistor density, higher performance and lower cost.

However, when making the integrated circuit smaller, the power supply also needs to be reduced.

In effect, a smaller amount of electrical charge is used to store the information, so that CMOS technology can be easily affected by single event transients (SETs). SET, a transient voltage disruption, can appear, for example, when the energetic particle strikes the semiconductor device’s sensitive region.

Such a situation can lead to soft errors in memory and logic devices, which means that the device does not have to be permanently damaged, but some data can be lost. For this reason, there is a need for a method enabling not only effective detection of SETs, but also their correction to improve the reliability of integrated circuits.

To meet this need, researchers from Universidade Federal do Rio Grande do Sul (UFRGS, Brazil) have proposed to use bulk built-in current sensors (bulk-BICS) to detect SETs. In the proposed solution, the BICS are not connected to the power lines of memory as proposed in previous approaches to current variations monitoring, but to bulk transistors. In such a way, the bulk-BICS are able to differentiate SETs from internal logic signals.

This is because when the particle strikes the semiconductor it generates current, which is much bigger than the bulk current under normal circuit operation. Hence, the solution enables detection of SET faults in digital combinatorial logic, which was not possible with the former approach.

The biggest advantage of the proposed solution is the possibility of SET detection, which can prevent the transient fault, thus increasing the reliability of the integrated circuits. The solution could be suitable for SET fault detection not only in memories, but also in digital combinatorial logic and mixed signal circuits.

At the current stage of the project, the solution has demonstrated proper detection of energetic particle strike. The researchers have also shown, through the use of device simulation, the possibility of using the combination of bulk-BICS together with BICS connected to the power lines for detection of multiple upsets in memory arrays. Detection of SETs appearing in periphery logics has also been demonstrated. The next step of the project would be related to the experimental verification of the solution. Hence, it will consist of designing, fabricating, and testing of the bulk-BICS integrated into the chip that is under the impact of energetic particles.

For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)21 680 3274, patrick.cairns@frost.com, <a href="http"//www.frost.com" target="_blank"> www.frost.com</a>

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