The continuous computational demands of artificial intelligence (AI) and machine learning (ML) workloads, cloud computing and data analytics deployed on traditional parallel attached memory have reached an efficiency plateau due to the limitations of increased memory channels on a processor. Microchip Technology has therefore announced the expansion of its serial-attached memory controller portfolio with the new SMC 2000 series of Compute Express Link (CXL)-based smart memory controllers that enable CPUs, GPUs and SoCs to utilise CXL interfaces to connect either DDR4 or DDR5 memory. This solution delivers more memory bandwidth and memory capacity per core, and lowers the overall total cost of ownership in the data centre.
The low-latency SMC 2000 16 x 32G and SMC 2000 8 x 32G memory controllers are designed to CXL 1.1 and CXL 2.0 specifications, DDR4 and DDR5 JEDEC standards and support PCIe 5.0 specification speeds. The SMC 2000 16 x 32G is currently the highest-capacity controller with 16 lanes operating at 32 GT/s and supporting two channels of DDR4-3200 or DDR5-4800, resulting in a significant reduction in the required number of host CPU or SoC pins per memory channel. Typical CXL attached memory modules include 512 GB of memory or more, providing an effective mechanism to increase the memory bandwidth available to processing cores.
“Microchip is excited to introduce our first CXL-based serial memory controller device to the market,” said Pete Hazen, corporate vice president of Microchip’s data centre solutions business unit. “We identified CXL as a disruptive technology early on and it was integral to the standard’s definition. Microchip’s continued presence in the memory infrastructure market underscores our commitment to improving performance and efficiency for a broad range of SoC applications to support the increasing memory requirements of high-performance data centre applications.”
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