Design Automation


HDL design environment addresses design creation and management issues

24 September 2003 Design Automation Industrial (Industry)

Mentor Graphics' HDL Designer Series 2003.1, the latest version of the design environment for the creation, development and management of complex ASIC and FPGA semiconductor designs, includes new design management, creation, analysis and documentation capabilities.

Today's multimillion gate semiconductors require a team design approach and rigorous data and process management. At the heart of the company's enhancements to HDL Designer Series is the design manager tool. This tool provides easy design navigation and the ability to search and organise data to aid in understanding design content and relationship of design data files and objects. Designers can sort, group and filter data based on any design unit attribute and instantly view any portion of the design hierarchy. In addition, a shortcut bar is included with quick access to common functions such as: project, explore, tasks and viewpoints.

New to the HDL Designer Series is DesignPad, a design-aware, fully customisable hardware description language (HDL) code editor. It allows users to access design data through a code browser that allows them to rapidly navigate HDL code.

Additional entry methods include interface-based design, a unique tabular design methodology for rapidly editing structural HDL for large and complex designs, and ModuleWare, which generates silicon-vendor-independent logic for a variety of common logic functions. HDL Designer Series 2003.1 also includes intuitive graphical editors, such as block diagrams, state machines, flow charts and truth tables.

Design re-use is a reality in all facets of semiconductor design. Through interface-based design, block diagrams and the ability to view the design hierarchy, users can visualise virtually every aspect of the design, speeding comprehension of the design.

With as much as 80% of design time spent in verification, methods to speed this integral process helps with strict time-to-market demands. This version works with HDL simulators including ModelSim to enhance their design analysis capabilities. Graphical and tabular design views in HDL Designer Series interact live during simulation.

More and more often design groups are now distributed. The HTML export documentation now enables global design teams to securely share and publish designs for design reviews and later reuse. Designers can share information with customers and partners, while controlling how much data is visible to shield proprietary or incomplete code.

For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, kobus@asic.co.za



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