DSP, Micros & Memory


Asynchronous SRAMs with ECC

20 May 2015 DSP, Micros & Memory

Cypress Semiconductor is sampling 4 Mb asynchronous SRAMs with error-correcting code (ECC). A hardware ECC block performs all error correction functions inline, without user intervention, delivering soft error rate (SER) performance of less than 0,1 FIT/Mb (one FIT is equivalent to one error per billion hours of device operation). The chips also include an optional error indication signal that indicates the correction of single-bit errors. They are available in three options: Fast, MoBL and Fast with PowerSnooze – an additional power-saving deep sleep mode that achieves 15 μA current. Each of the options is offered in industry standard x8 and x16 configurations, and operate at 1,8 V, 3 V and 5 V.

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