Programmable Logic


FPGA development suite for Pentek recorders

30 June 2020 Programmable Logic

Pentek’s ArchiTek FPGA Development Suite is a new product for adding custom IP to select Pentek Talon recording systems. ArchiTek is a comprehensive development environment that enables engineers to add FPGA IP to recording systems, such as threshold detection, spectral filtering, digital down-conversion, signal classification, demodulation and many other digital signal processing techniques.

Developing custom IP for an FPGA requires an architecture that protects the user from custom IP development pitfalls such as breaking the existing IP and corresponding recording software. ArchiTek harnesses Pentek’s Navigator FPGA Development Kit (FDK) and board support package (BSP) to provide a development environment that steps engineers through the process of integrating custom IP into the recorder.

Along with the Navigator FDK, ArchiTek provides the foundation and example projects for adding IP to user blocks and creating additional data-path branches from existing data streams. The structured design protects the recorder’s standard functionality, reducing development time and risk.

Customers can now add FPGA IP to a recorder for real-time, on-the-fly digital signal processing during the data acquisition process, greatly reducing the time associated with post-processing recorded data. Recording of only critical data also greatly reduces transfer rates, recording capacity requirements and data offload time.

Using ArchiTek, FPGA developers can add additional recording channels to the system, so users can record both processed and unprocessed data simultaneously. ArchiTek provides extensive documentation and tutorials to assist developers through the customisation process, reducing both risk and development time.

ArchiTek use-case examples

Many digital communication protocols use spread-spectrum techniques, in which many signal channels are spread across the same frequency span using pseudo-random sequence encoding. Instead of recording the entire frequency span, ArchiTek allows one signal of interest to be extracted using a custom FPGA block so that only that signal is delivered for recording. This can reduce the recording rate and storage capacity by orders of magnitude.

Another SIGINT monitoring application might require signal classification and time stamping of each received transmission. By suitably configuring the classification algorithm within the FPGA using ArchiTek, only the key parameters of each signal need to be recorded instead of the signals themselves, thus dramatically extending the useful mission time. This strategy of real-time processing at the front end also reduces or eliminates post-processing tasks.


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