Electronics Technology

IBM shrinks chip geometries to 2 nm

26 May 2021 Electronics Technology

The new 2 nm nanosheet architecture, developed less than four years after IBM announced its milestone 5 nm design, will be able to fit up to 50 billion transistors on a chip the size of a fingernail.

The current state-of-the-art in terms of semiconductor chip geometries has been superseded by a new breakthrough coming out of IBM’s world renowned research division. Currently the ‘process node’ most commonly used commercially is 7 nm, with TSMC (Taiwan Semiconductor Manufacturing Company, the world’s largest semiconductor contract fabrication company) pushing chips out at a rate of almost half a billion per year. The nascent 5 nm node is out there and has been commercialised (by the likes of TSMC) but is still too expensive for any but the most demanding applications.

Now the boundaries have been pushed yet further, with IBM’s development of the world’s first chip to employ 2 nm nanosheet technology. Increasing the number of transistors per chip can make them smaller, faster, more reliable and more efficient. IBM’s new 2 nm architecture, developed less than four years after it announced its milestone 5 nm design, will allow the 2 nm chip to fit up to 50 billion transistors on a chip the size of a fingernail.

More transistors on a chip also means processor designers have more options to infuse core-level innovations to improve capabilities for leading-edge workloads like AI and cloud computing, as well as new pathways for hardware-enforced security and encryption. IBM is already implementing other innovative core-level enhancements in the latest generations of IBM hardware, like IBM POWER10 and IBM z15.

Demand for increased chip performance and energy efficiency continues to rise, especially in the era of hybrid cloud, AI and the Internet of Things. IBM’s new 2 nm chip technology addresses this growing demand and is projected to achieve 45% higher performance, or 75% lower energy use, than today’s most advanced 7 nm node chips.

“The IBM innovation reflected in this new 2 nm chip is essential to the entire semiconductor and IT industry,” said Darío Gil, senior vice president and director of IBM Research. “It is the product of IBM’s approach of taking on hard tech challenges and a demonstration of how breakthroughs can result from sustained investments and a collaborative R&D; ecosystem approach.”

By way of example, the potential benefits of these advanced 2 nm chips could include:

• Quadrupling cellphone battery life, only requiring users to charge their devices every four days.

• Slashing the carbon footprint of data centres, which account for 1% of global energy use. Changing all of their servers to 2 nm-based processors could potentially reduce that number significantly.

• Drastically speeding up a laptop’s functions, ranging from quicker processing in applications, to assisting in language translation more easily, to faster Internet access.

• Contributing to faster object detection and reaction time in autonomous vehicles like self-driving cars.

This latest breakthrough builds on decades of IBM leadership in semiconductor innovation. The company’s semiconductor development efforts are based at its research lab located at the Albany Nanotech Complex in Albany, New York, where IBM scientists work in close collaboration with public and private sector partners to push the boundaries of logic scaling and semiconductor capabilities.

This collaborative approach to innovation makes IBM Research Albany a world-leading ecosystem for semiconductor research and creates a strong innovation pipeline, helping to address manufacturing demands and accelerate the growth of the global chip industry.

IBM’s legacy of semiconductor breakthroughs also includes the first implementation of 7 nm and 5 nm process technologies, single cell DRAM, the Dennard Scaling Laws, chemically amplified photoresists, copper interconnect wiring, silicon-on-insulator technology, multicore microprocessors, high-K gate dielectrics, embedded DRAM and 3D chip stacking.

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