Xilinx recently introduced Vivado ML Editions, the industry’s first FPGA EDA tool suite based on machine learning (ML) optimisation algorithms, as well as advanced team-based design flows for design time and cost savings. Vivado ML Editions delivers 5x faster compile time and quality of results (QoR) improvements on average 10% for complex designs, compared to the current Vivado HLx Editions.
Vivado ML Editions enables ML-based algorithms that accelerate design closure. The technology features ML-based logic optimisation, delay estimation and intelligent design runs, which automates strategies to reduce timing closure iterations.
Xilinx is also introducing the concept of an Abstract Shell, which allows users to define multiple modules within the system to be compiled incrementally and in parallel. This enables an average compile time reduction of 5x, and up to 17x, compared to traditional full system compilation. Abstract Shell also helps protect a customer’s IP by hiding the design details outside of the modules, critical for applications like FPGA-as-a-Service and value-added system integrators.
In addition, Vivado ML Editions improves collaborative design with Vivado IP Integrator, which enables modular design using the new ‘block design container’ feature. This capability promotes a team-based design methodology and allows for a divide-and-conquer strategy to handle large designs with multisite cooperation.
Unique adaptability features like Dynamic Function eXchange (DFX) enable more efficient use of silicon resources by loading custom hardware accelerators, dynamically at runtime over-the-air. With the ability of DFX to load design modules in a few milliseconds, it opens up new use cases such as a car swapping different vision algorithms during processing of a frame, or a genomic analysis swapping different algorithms in real-time as it sequences DNA.
AMD Vivado Design Suite 2025.1
Design Automation
AMD Vivado Design Suite 2025.1 is here, and now with support for AMD Spartan UltraScale+ and next-generation Versal devices.
Read more...MCX C Series development board Avnet Silica
DSP, Micros & Memory
The FRDM-MCXC444 is a compact and scalable development board for rapid prototyping of MCX C444 MCU from NXP Semiconductors.
Read more...Cutting-edge hybrid capacitors Avnet Silica
Passive Components
Panasonic Industry recently announced the launch of the ZVU Series Hybrid Capacitors, a cutting-edge solution tailored to meet the escalating demands of advanced electronic systems.
Read more...Webinar: Designing in a connected environment
Design Automation
With Altium Designer and its data management platform, the team will always be up to date with the latest design documents and be able to comment on schematic, PCB, BOM and assembly drawings.
Read more...ST’s graphical no-code design software
Design Automation
MEMS-Studio is a complete desktop software solution designed to develop embedded AI features, evaluate embedded libraries, analyse data, and design no-code algorithms for the entire portfolio of ST’s MEMS sensors.
Read more...Hardware quantum resistance to embedded controllers Avnet Silica
DSP, Micros & Memory
To help system architects meet evolving security demands, Microchip Technology has developed its MEC175xB embedded controllers with embedded immutable post-quantum cryptography support.
Read more...Bluetooth module brilliance Avnet Silica
Telecoms, Datacoms, Wireless, IoT
Following the company’s popular PAN1780, the PAN1783 Bluetooth 5.3 Low Energy (LE) module from Panasonic is based on the Nordic nRF5340 single chip controller.
Read more...NXP’s latest wireless chip solution Avnet Silica
Telecoms, Datacoms, Wireless, IoT
NXP’s IW610 wireless chip solution features a 1x1 dual-band Wi-Fi 6 radio subsystem, offering improved network efficiency, reduced latency and extended range.
While every effort has been made to ensure the accuracy of the information contained herein, the publisher and its agents cannot be held responsible for any errors contained, or any loss incurred as a result. Articles published do not necessarily reflect the views of the publishers. The editor reserves the right to alter or cut copy. Articles submitted are deemed to have been cleared for publication. Advertisements and company contact details are published as provided by the advertiser. Technews Publishing (Pty) Ltd cannot be held responsible for the accuracy or veracity of supplied material.