Editor's Choice

Improving precision ADC signal chain design time with CTSDs

29 September 2021 Editor's Choice

In many digital processing applications and algorithms, the demand to have better resolution and precision for all converter technologies has increased over the last two decades. The limited resolution/precision of analog-to-digital converters (ADCs) was enhanced by using an external digital controller that would extract and deliver more precise results using software techniques such as averaging and optimised filtering schemes.

To reduce extensive postprocessing at the digital microcontroller or digital signal processor (DSP), designers could use a high-performance precision ADC. This would reduce optimisation time at the digital side and a lower-cost microcontroller or DSP could also be considered.

The applications and markets for precision ADCs are widespread:

• Industrial instrumentation: vibration analysis, temperature/pressure/strain/ flow measurements, dynamic signal analysis, acoustic analysis.

• Medical instrumentation: electrophysiology, blood analysis, electrocardiogram (EKG/ECG).

• Defence applications: sonar, telemetry.

• Test and measurement: audio test, hardware in loop, power quality analysis.

The analog input signal to be processed by an ADC could be a sensor signal with voltage, current output, or a feedback control loop signal with bandwidth ranging from DC to a few hundred kHz. The ADC digital output format and rate are dependent on the application and postprocessing required by the subsequent digital controller. In general, signal chain designers follow the Nyquist sampling theorem and program the ADC’s output data rate (ODR) for the digital controller to be at least twice the input frequency. Most ADCs provide the flexibility to tune the output data rate based on the signal frequency band of interest.

For currently available ADCs, there are several signal conditioning stages involved before the ADC can interact with the input signal. Signal conditioning circuits with stringent requirements need to be designed and tailored around specific and individual ADC technologies to ensure that ADC data sheet performance can be achieved.

A signal chain designer’s job doesn’t stop after the selection of the ADC. Considerable time and effort are often required to design and fine-tune this surrounding periphery. Analog Devices provides a high level of technical support in the form of design simulation tools and models to overcome most of these inherent design challenges.

A new approach: Easing the design journey with CTSD architecture

Continuous-time sigma-delta (CTSD) architecture, which has been predominantly used in audio and high-speed ADCs, is being tailored for precision applications to achieve the highest precision while leveraging its unique signal chain simplification properties. The advantages of this architecture remove the burdens involved with designing the periphery. Figure 2 shows a small snippet of how current ADC signal chains can be simplified and shrunk by 68% by using this new solution to enable high channel densities.

To illustrate the simplification that CTSD ADC technology brings to the signal chain, this article highlights some of the key challenges involved in incumbent signal chain design for general applications, as well as showing how CTSD ADCs ease these challenges.

So, let’s start with a few design steps involved in incumbent signal chains, with the very first task being the selection of the right ADC to best fit the targeted application.

Step 1: Selecting the ADC

When selecting from the wide range of ADCs that are available, important considerations are resolution and accuracy, signal bandwidth, ODR, signal type and the range to be processed. Generally, in most applications, digital controllers require their algorithms to process amplitude, phase or frequency on the input signal.

To accurately measure any of the previous factors, the errors added in the process of digitisation need to be minimal. The major errors and their corresponding measurement terminology are detailed in Table 1.

The performance metrics in Table 1 are related to signal amplitude and frequency and are generally termed as AC performance parameters.

For DC or near-DC applications such as power metering dealing with 50 Hz to 60 Hz input signals, ADC errors such as offset, gain, INL and flicker noise would have to be accounted for. These DC performance parameters also require a certain level of temperature stability relating to an application’s intended use.

Analog Devices provides a wide range of industry-leading, high-performance ADCs to meet system requirements of several applications, be they precision-based, speed-based, or based on a restricted power budget. Just comparing one set of ADC specifications to another is not the way to choose an ADC. The overall system performance and design challenges must be considered and that’s where the choice of ADC technology or architecture comes into play.

There are two broad classifications of ADC architectures that are traditionally preferred. The most popular is the successive approximation register (SAR) ADC, which follows the simple Nyquist theorem. It states that a signal can be reconstructed if sampled at twice its frequency. The advantages of SAR ADCs are excellent DC performance and small form factors, with low latency and power consumption scaling with ODR.

The second technology choice is a discrete-time sigma-delta (DTSD) ADC, which works on the principle that the greater the number of samples, the less information is lost. So the sampling frequency is much higher than the stated Nyquist frequency, a scheme referred to as oversampling. An added advantage from this architecture is that the errors added due to sampling are minimised in the frequency band of interest. Because of this, DTSD ADCs have both excellent DC and AC performance but a higher latency.

Figure 3 shows an illustration of the typical analog input bandwidths of both SAR and DTSD ADCs, with some popular product choices at various speeds and resolution. The ‘Precision Quick Search’ feature can also be referenced to help in your choice of ADC.

Additionally, a new class of precision ADCs are now available. These are based on CTSD ADCs that are on par with the performance of DTSD ADCs but they are unique with regard to simplifying the entire signal chain design process. The challenges highlighted in the next few design steps of an incumbent signal chain can be addressed by this new ADC family.

Step 2: Interfacing the input to the ADC

Sensors whose outputs are to be processed by the ADC may have very high sensitivity. Designers must have a good understanding of the ADC input structure to which the sensor will be interfaced to ensure ADC errors don’t mask or distort the actual sensor signal.

In conventional SAR DTSD ADCs, the input structure is known as the switched capacitor sample-and-hold circuit, as shown in Figure 4. At every sampling clock edge when the sample switch changes its ON/OFF state, finite current demand needs to be supported to charge or discharge the hold capacitor to a new sampled input value. This current demand needs to be supplied by the input source, which in our case of discussion is the sensor. Additionally, the switch itself has some on-chip parasitic capacitors that inject some charge back into the source, which is called charge injection kickback. This added error source also needs to be absorbed by the sensor to avoid corruption of the sensor signal.

Most of the sensors are incapable of providing such a magnitude of currents, indicating that they fall short of driving switching circuitry directly. In a different scenario, say even if a sensor can support these current demands, the sensor’s finite impedance would add an error at the ADC input. The charge injection current is a function of input and this current causes an input-dependent voltage drop across the sensor impedance. As shown in Figure 4a, the input of the ADC is then in error. One solution to solve these issues is to place a driving amplifier between the sensor and ADC, as shown in Figure 4b.

Now we need to set the criteria for this amplifier. First and foremost, the amplifier should support the charging current and absorb the charge injection kickback. Next, this amplifier’s output needs to be fully settled at the end of the sampling edge so that the ADC samples input without added errors. This means the amplifier should have the capability to provide instantaneous current steps that map to having a high slew rate and provide a fast settling response to these transient events, which maps to having high bandwidth. As the sampling frequency and resolution of the ADC increases, meeting these requirements becomes critical.

The big challenge for designers, especially those who work with medium-bandwidth applications, is to identify the right amplifier for the ADC. As indicated earlier, Analog Devices provides a set of simulation models and precision ADC driver tools to ease this step, but for a designer, it is an added design step to achieve the data sheet performance of the ADC. Some of the new-age SAR and DTSD ADCs have mitigated this challenge by using novel sampling techniques to completely reduce the transient current demand, or by having an integrated amplifier. But either solution limits the range of signal bandwidth or penalises ADC performance.

CTSD ADCs address this challenge by providing an easy-to-drive resistive input instead of a switched capacitor input. This shows that there are no hard requirements of high-bandwidth, large slew-rate amplifiers. If sensors can directly drive this resistive load, they can be directly interfaced to a CTSD ADC; otherwise any low-bandwidth, low-noise amplifier could be interfaced between a sensor and a CTSD ADC.

Step 3: Interfacing the reference to the ADC

The challenge involved with interfacing to a reference is similar to input interfacing. The reference input for conventional ADCs is also a switched capacitor. At every sampling clock edge, the reference source needs to charge the internal capacitors, thus demanding large switching current with good settling time.

The reference ICs available cannot support large switching current demand and have limited bandwidth. The second interfacing challenge is that noise from these references is large in comparison to an ADC’s noise. To filter this noise, a first-order RC circuit is used. On one hand we are band-limiting the reference for noise, while on the other hand we are demanding fast settling time. These are two opposing requirements to satisfy. For this reason, a low-noise buffer is used to drive the ADC reference pin, as shown in Figure 5b. Based on the sampling frequency and resolution of an ADC, the slew rate and bandwidth of this buffer is decided.

Again, like with our precision input driver tools, Analog Devices has tools to simulate and select the correct reference buffers for an ADC. And similar to input, some of the new-age SAR and DTSD ADCs also have the option of an integrated reference buffer, but they come with performance and bandwidth limitations.

This design step can be completely skipped by using a CTSD ADC as it provides a new, easy option for driving a resistive load that doesn’t require such a high-bandwidth, large slew-rate buffer. The reference IC with low-pass filter can be directly interfaced to the reference pin.

Step 4: Making a signal chain immune to interference

Sampling and digitising a continuous signal causes loss of information, which is termed quantisation noise. The sampling frequency and number of bits set the performance limit for an ADC architecture.

After addressing the performance and interfacing challenges for the reference and input, the next struggle is to address the issue of high-frequency (HF) interferers/noise-folding into the low-frequency bandwidth of interest. This is termed aliasing or folding back. These reflected images of the HF or out-of-band interferers into the bandwidth of interest cause signal-to-noise ratio (SNR) degradation.

Citing the sampling theorem, any tone around the sampling frequency folds back in-band, as illustrated in Figure 6, which causes unwanted information or error in the frequency band of interest.

One solution to mitigate the effect of foldback is to use a type of low-pass filter known as an antialiasing filter (AAF) to attenuate the unwanted interferer’s magnitude such that when this attenuated interferer folds back in-band, the desired SNR is maintained. This low-pass filter is generally incorporated with a driver amplifier, as shown in Figure 7.

When designing this amplifier, the biggest challenge is finding a balance between faster settling and the low-pass filtering requirements. An added challenge is that this solution needs to be fine-tuned for each application requirement, which limits the adoption of single-platform design across various applications. Analog Devices has many antialiasing filter tool designs to help designers overcome this challenge.

This immunity to interference is addressed by the inherent alias rejection property of the CTSD ADC itself, a feature that is unique only to CTSD ADCs. The AAF is not required for ADCs with this technology. So, we would be one step nearer to directly interfacing a CTSD ADC to a sensor without much effort.

Step 5: Selecting the ADC clock frequency and the output data rate

Next, let’s discuss the clock requirements for the two classes of traditional ADCs we have discussed. The DTSD is an oversampled ADC, which means that the ADC is sampled at a higher-than-Nyquist sampling rate. But giving ADC oversampled data directly to the external digital controller implies we are overloading it with lots of redundant information. In an oversampled system, the core ADC output is decimated using on-chip digital filters that enable the final ADC digital output at a lower data rate, which is usually twice the signal frequency.

For DTSD ADCs, the designer needs to plan for the provision of the high-frequency sampling clock for the core ADC and program the desired output data rate. The ADC will give a final digital output at this desired ODR and the ODR clock. A digital controller uses this ODR clock to clock in the data.

Next, we address the clock requirements of SAR ADCs, which usually follow the Nyquist theorem. Here, the sampling clock of the ADC is provided by a digital controller and the clock also acts as an ODR. But there is less flexibility in the timing of this clock as the sample-and-hold timing needs to be well controlled to get optimum performance from the ADC, which also indicates that the timing of the digital output needs to be well aligned with these requirements.

In understanding the clock requirements of both these architectures, we see that the ODR is coupled to the sampling clock of the ADC, which is a limitation in many systems where ODR can drift or change dynamically, or needs to be tuned to the analog input signal frequency.

The CTSD ADC couples with a novel asynchronous sample rate converter (ASRC) that resamples the core ADC data at any desired ODR. The ASRC also enables designers to granularly set the ODR at any frequency and go beyond the age-old restriction of limiting ODR to a multiple of the sampling frequency. The frequency and timing requirements of ODR are now purely a function of the digital interface and completely decoupled from the ADC sampling frequency. This feature eases digital isolation design for signal chain designers.

Step 6: Interfacing with the external digital controller

Traditionally, there are two types of data interface modes for ADCs to communicate with the digital controller. One involves the ADC acting as a host, providing the digital/ODR clock and deciding on the clock’s edges for the digital controller to clock-in the ADC data. The other type is hosted mode (receiver mode), in which the digital controller is the host, provides the ODR clock and decides the clock edges at which the ADC data will be clocked in.

Continuing from Step 5, if a designer selects a DTSD ADC, the ADC acts as host for the ensuing digital controller since the ADC provides the ODR clock. If an SAR ADC is selected, the digital controller needs to provide the ODR clock, implying that SAR ADCs are always configured as a hosted peripheral. So, the obvious limitation is that once an ADC architecture is chosen, the digital interface is restricted to being in host mode or hosted mode. Currently there is no flexibility in choosing the interface, regardless of ADC architecture.

The novel ASRC that has been coupled with a CTSD ADC enables designers to independently configure the ADC data interface mode.This opens up a whole new opportunity for applications where high-performing ADCs can be configured in any mode suitable for the digital controller of the application, irrespective of ADC architecture.

Putting it all together

Figure 9 shows the building blocks of a traditional signal chain with an analog front end (AFE) comprising an ADC input driver, an alias rejection filter and a reference buffer that can be drastically simplified by a CTSD ADC. Figure 10a illustrates an example signal chain with a DTSD ADC that requires significant design effort to fine-tune and derive the data sheet performance of the ADC. To ease the customer journey, Analog Devices has reference designs that can be reused or retweaked for various applications for these ADCs.

Figure 10b shows a signal chain with a CTSD ADC with its simplified analog input front end because its ADC core does not have a switch capacitor sampler at the input and reference. The switch sampler is moved to a later stage of the ADC core, making the signal input and reference input purely resistive. This results in an almost non-sampling ADC, making it a class of its own. Also, the signal transfer function of this class of ADCs mimics the antialiasing filter response, which means it inherently attenuates noise interferers. With CTSD technology, the ADC is reduced to an easy plug-and-play component.

In summary, CTSD ADCs simplify signal chain design while achieving a system solution with the same performance level as a traditional ADC signal chain, along with offering the following advantages:

• Provides an alias-free, low-latency signal chain with excellent channel-to-channel phase matching.

• Simplifies the analog front end with no added step of selection and fine-tuning of high-bandwidth input and reference driver buffers, enabling higher channel density.

• Breaks barrier of ODR being a function of the sampling clock.

• Gives independent control of the interface to an external digital controller.

• Improves the signal chain reliability rating, which is a direct result of periphery component reduction.

• Reduces size and has a 68% reduction in bill of material, leading to faster time to market for customers.

For more information contact Conrad Coetzee, Altron Arrow, +27 11 923 9600, ccoetzee@arrow.altech.co.za, www.altronarrow.com


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