A webinar titled ‘Maximise design productivity using Vivaldo ML tools with SystemVerilog’ will be hosted by AMD Xilinx’s authorised training partner at 11:00 CAT on 17 August 2022.
The webinar will explore the features of SystemVerilog that are useful for RTL synthesis using Vivado ML Tools and how the RTL SystemVerilog language constructs have been optimised for productivity and reliability. The session will begin with the basic principles of RTL coding style in SystemVerilog, then will focus on the language features that allow FPGA hardware designers to work efficiently while at the same time avoiding synthesis pitfalls.
The 1-hour webinar will conclude with a Q&A session.
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