Silicon Laboratories has introduced a range of universal clock buffers capable of replacing LVPECL, LVDS, CML, HCSL and LVCMOS buffers with a single IC, eliminating the need for multiple fixed-format buffers.
The new Si533xx family integrates common clock tree functions including clock distribution, clock muxing, clock division, format translation and level translation. Based on a patented low-phase-noise clock driver architecture, the ICs feature ultra-low additive jitter with guaranteed maximum jitter specifications, simplifying clock tree design and providing designers more jitter margin for other devices.
The clock buffers are purpose-built to address the demanding requirements of communications, data centre, wireless infrastructure, broadcast video and embedded computing applications.
Clock outputs are split into two independent banks. The signal format of each bank is user-selectable through simple pin-strapping, providing developers with an array of options. Both banks have dedicated supply voltage pins independent of the core voltage, enabling simple voltage-level translation.
The devices’ universal input stage accepts two differential or single-ended inputs, and a low-noise 2:1 input mux supports glitchless switching, eliminating the risk of runt pulses being transferred to the device outputs during an input clock switch. In addition, some of the buffers support individual output enable pins for each output clock, providing control flexibility.
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