Altera unveiled its Spectra-Q engine, a new technology at the heart of the company’s proven Quartus II software, to improve design productivity and time-to-market for next-generation programmable devices.
It provides compile time improvements, versatile and fast-tracked design entry, and drop-in IP integration to allow customers to design and implement at higher levels of abstraction for faster design cycles.
Spectra-Q features faster algorithms and allows for incremental design changes without needing to perform a full design compile. It also features a hierarchical database that enables users to preserve placement and routing information of IP blocks while making changes in other parts of the design. This helps ensure stable designs, eliminates unnecessary timing closure efforts and reduces compile times. The new engine also includes a common high-level design compiler for better quality of results and tighter integration between the Quartus II software and a variety of different front-end tools.
Built on top of the Spectra-Q engine is an industry-first platform design tool called BluePrint, which allows designers to perform architectural exploration and assign interfaces with greater efficiency. The tool reduces design iterations by 10 times by allowing designers to explore and create legal I/O placements upfront with real-time fitter checking. The tool also includes a clock and core planning feature that greatly reduces the number of design iterations needed for timing closure.
The engine fast-tracks design entry for software, hardware and DSP designers alike. With multiple versatile design flows, designers can target FPGAs with greater efficiency in the language or design environment they prefer. In addition to providing support for the latest HDL languages, the new engine is designed to support Altera’s new A++ Compiler for HLS (high level synthesis) to create IP cores from C or C++ which boosts productivity through faster simulation and IP generation.
The unveiling of Spectra-Q coincided with Altera’s release of the new version 15.0 of its Quartus II software. It introduces new Hybrid Memory Cube and HDMI 2.0 MegaCores for the company’s Arria 10 FPGAs and SoCs. The portfolio also includes an upgrade in features and device support for the company’s popular JESD204B core to update Arria V support to 9,255 Gbps as well as Cyclone V support up to 5 Gbps.
IP debug toolkits for external memory interfaces (EMIF) and PCI Express are also available to help designers rapidly prototype and expedite qualifications, with additional access points to perform test and debug on IP cores.
The Spectra-Q engine is available as an early access programme. Both the Subscription Edition and the free Web Edition of Quartus II software v15.0 are now available for download at www.altera.com/download.
For more information contact EBV Electrolink, +27 (0)21 402 1940, [email protected], www.ebv.com
| Tel: | +27 11 236 1900 |
| Email: | [email protected] |
| www: | www.ebv.com |
| Articles: | More information and articles about EBV Electrolink |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version