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RFSoC architecture by Xilinx
14 November 2018, Telecoms, Datacoms, Wireless, Programmable Logic
Xilinx rolled out its Zynq UltraScale+ RFSoC family, an architecture integrating the RF signal chain into a system-on-chip (SoC) for high-performance RF applications.
Based on the 16 nm UltraScale+ MPSoC architecture, the chips monolithically integrate RF data converters for up to 50% to 75% system power and footprint reduction, and soft-decision forward error correction (SD-FEC) cores to meet 5G and DOCSIS 3.1 standards.
Devices in the family feature eight 4 GSps or sixteen 2 GSps 12-bit ADCs; eight to sixteen 6,4 GSps 14-bit DACs; integrated SD-FEC cores with LDPC and Turbo codecs for 5G and DOCSIS 3.1; ARM processing subsystem with quad-core Cortex-A53 and dual-core Cortex-R5s; 16 nm UltraScale+ programmable logic with integrated Nx100G cores; and up to 930 000 logic cells and over 4200 DSP slices.
Applications include remote radio heads for massive-MIMO, millimetre-wave mobile backhaul, 5G baseband, fixed wireless access, Remote-PHY nodes for cable, radar, test and measurement, satcom, and milcom/airborne radio.
For more information contact Erich Nast, Avnet South Africa, +27 11 319 8600, erich.nast@avnet.eu, www.avnet.co.za |
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