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RISC-V based FPGA architecture
14 November 2018, Programmable Logic

Microchip, via its Microsemi Corporation subsidiary, announced an extension to its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs at the RISC-V Summit during December 2018. The new family combines the low-power, mid-range PolarFire FPGA family with a complete microprocessor subsystem based on the open, royalty-free RISC-V instruction set architecture (ISA).

The new architecture brings real-time deterministic asymmetric multiprocessing (AMP) capability to Linux platforms in a multi-core coherent central processing unit (CPU) cluster. Developed in collaboration with SiFive, it features a flexible 2 MB L2 memory subsystem that can be configured as a cache, scratchpad or a direct access memory. This allows designers to implement deterministic real-time embedded applications simultaneously with a rich operating system for a variety of thermal- and space-constrained applications in collaborative, networked IoT systems.

In a new era of computing driven by the convergence of 5G, machine learning and the Internet of Things (IoT), embedded developers need the richness of Linux-based operating systems. These must meet deterministic system requirements in ever lower-power, thermally constrained design environments, while addressing critical security and reliability requirements.

Traditional system-on-chip FPGAs blend reconfigurable hardware with Linux-capable processing on a single chip to provide developers with ideal devices for customisation, yet consume too much power, lack proven levels of security and reliability, or use inflexible and expensive processing architectures.

PolarFire SoC includes extensive debug capabilities including instruction trace, 50 breakpoints, passive run-time configurable Advanced eXtensible Interface (AXI) bus monitors and FPGA fabric monitors, in addition to Microchip’s built-in two-channel logic analyser, SmartDebug.

The architecture includes reliability and security features, such as single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a differential power analysis (DPA)-safe crypto core, defence-grade secure boot and 128 Kb Flash boot memory.

Evaluation and design with PolarFire SoC are supported by the antmicro Renode system modelling platform, which is now integrated with Microchip’s SoftConsole IDE for embedded designs targeting PolarFire SoCs. A PolarFire SoC development kit is also available, consisting of the PolarFire FPGA-enabled HiFive Unleashed Expansion Board and SiFive’s HiFive Unleashed Development Board with its RISC-V microprocessor subsystem.

As part of the same announcement, Microchip launched a new Mi-V Embedded Experts Program, a worldwide partner network to assist customers in hardware/software designs for PolarFire SoC. The addition of this programme ensures support throughout the entire lifecycle of customer products and helps to jump-start designs and shorten time to market. Members also get access to direct technical support and early access to development platforms and silicon.

For more information contact Dirk Venter, Altron Arrow, +27 11 923 9600, dventer@arrow.altech.co.za, www.arrow.altech.co.za


Credit(s)
Supplied By: Altron Arrow
Tel: +27 11 923 9600
Fax: +27 11 923 9884
Email: info@arrow.altech.co.za
www: www.altronarrow.com
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Further reading:

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