Atmel has launched what it calls a 'Logic doubling' initiative. The goal is to inform programmable logic designers of the advantages and extra value in the enhanced features of the company's ATF15xx family of complex programmable logic devices (CPLDs), which Atmel says has been further enhanced by its second generation fitter software.
"Atmel's ATF15xx CPLD family provides enhanced I/O connectivity and logic utilisability," said Jim Fahey, Atmel Director of EPLD Products. "Atmel's Logic Doubling architecture combined with Atmel's second-generation device fitters, extends CPLD place and route efficiency. Atmel CPLDs more flexible routing and denser packing of logic can stretch logic resources in some cases to 200% or more of typical CPLDs."
To back up these claims, Atmel has prepared a White Paper and a set of Reference Designs, and made them available on its website. PLD designers are encouraged to 'prove it to themselves' by registering on the Atmel website using the special URL given in the ads and banners. The PLD designer can then click through to download a White Paper, Reference Designs, second generation fitters, free Atmel PLD design software, and order ATF15xx product samples.
"Typical CPLDs use up a whole macrocell to add more than one layer of logic," continued Fahey. "At Atmel, our PLD architects took care to retain as much I/O connectivity and logic reusability as possible, introducing the 100% connected ATF1500 with 32 enhanced Macrocells in 1996. The ATF1502 has 32 macrocells, the ATF1504 64 macrocells, and the ATF1508 has 128 macrocells."
"The White Paper shows how our 128-macrocell ATF1508 can provide up to 256 latches compared to only 128 latches for a typical 128-macrocell CPLD," Fahey continued. "And, 'Logic doubling' is not just for register and latch intensive applications. Our 32-macrocell ATF1502 can swallow four 8 bit PWM modulators, including the required four digital-to-analog converters and an 8 bit bus interface. A typical CPLD family would need 64 macrocells, a larger and more expensive alternative."
Using these examples and tools, the PLD designer can then apply 'Logic doubling' techniques to new product designs, obtaining the benefits of more features in a smaller, and possibly less expensive chip or spare logic resources for future revisions and reduced risk of PCB re-spin.
For further information contact Arrow Altech Distribution (011) 923 9600, Avnet Kopp (011) 444 2333, Atmel SA 082 894 7223.
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