6 million gate design accelerated 16-fold with help of hardware acceleration

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2 July 2003 News

Aldec, a pioneer in mixed language simulation and advanced design tools for FPGA and ASICs, in conjunction with customised embedded systems service provider, Amirix Systems, announced that Amirix's recent embedded design that exceeded 6 million FPGA gates was accelerated over 16x by using Aldec's hardware acceleration product, Riviera-IPT.

Riviera-IPT is a PCI-based circuit board system installed on a workstation, PC or server running under UNIX, Linux or Windows NT/2000/XP operating system. There are several configurations of Riviera-IPT available, depending on the design's density. Configurations that include microprocessor support are also available.

With Riviera-IPT, Amirix said that it was not only able to better debug its design faster and more efficiently, but during the project's development, the design team at Amirix was able to make modifications to the design during the development process and quickly see how such changes will ultimately affect the end-device. The incorporation of hardware verification leads to a more flexible development process because changes can be tested and applied much faster than in a software environment alone.

Riviera-IPT is a software/hardware co-verification solution that allows designers to designate that certain modules of the design be placed into hardware while new portions of the design continue to reside in software. The design in its entirety can ultimately be placed in hardware for realtime runs. Riviera-IPT comes in various configurations and daughter board expansion options to best fit the needs of each designer.

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6 million gate design accelerated 16-fold with help of hardware acceleration

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