Lattice Semiconductor has released the 5 V ispLSI 1000EA family of high-density, in-system programmable (ISP) programmable logic devices (PLDs). This family consists of four family members including the ispLSI 1016EA, 1024EA, 1032EA, and 1048EA with densities ranging from 64 to 192 macrocells.
The ispLSI 1000EA family represents Lattice's third generation ispLSI 1000 family, with added features. Lattice claims the 1032EA, at 4 ns Tpd and 200 MHz, and the 1048EA, at 5 ns and 170 MHz, are each 2 ns faster than the nearest competitive offering - representing a 33% performance improvement.
"With over 50% of system designers still using 5 V supplies, Lattice remains committed to providing the blazing performance required to meet the needs of this marketplace," said Steve Stark, Director of Product Marketing at Lattice. "The products introduced today beat the fastest competitive offering by at least 33%. If you are designing a high-performance 5 V system, Lattice is the clear choice."
Coupled with high performance, the ispLSI 1000EA family offers the following enhanced features: IEEE-1149.1 boundary scan test (JTAG); ispJTAG in-system programming via IEEE-1149.1 test access port; user selectable 5 V or 3,3 V I/Os; open drain output option; rapid programming times.
Another significant advantage is that programming times for all ispLSI 1000EA family members are less than two seconds, reducing development and debug costs, as well as manufacturing production costs. Lattice's ispLSI 1000EA devices are highly suited for implementing fast counters, state machines, and address decoders.
For further information about Lattice Semiconductor
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