Increased performance for ASIC verification solution plus new support for SystemC
16 July 2003
Design Automation
In April, Aldec released Riviera 2003.03 with increased performance, new debugging features and introduced support for SystemC. The Riviera product is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology, used by ASIC and high-density FPGA designers who want to use new generation system-on-chip methodologies.
Aldec says that Riviera's optimised simulation compiler reduces compilation time by as much as 50% over previous versions. More efficient memory allocation substantially reduces the amount of memory required during both compilation and simulation, further accelerating overall run times.
In addition to VHDL, Verilog and mixed HDL simulation in Riviera, Aldec added the ability to co-simulate SystemC in version 2003.03. Co-simulation support is especially useful for the growing number of system-level designs incorporating C components and testbenches. Debugging is improved with toggle coverage and assertion support. Both features offer more detailed information and help designers improving the overall quality of the code.
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