FPGA synthesis software optimises area so reducing costs
19 November 2003
Electronics Technology
Synplicity extended the timing-driven performance advantage of its FPGA synthesis software, Synplify Pro that offers users the ability to more easily optimise for area after their speed goal is met, potentially reducing device size and saving money in device costs. Additional optimisations were also added to the software to further its performance quality of results (QoR), including the addition of register re-timing for Actel ProASIC and ProASIC Plus FPGAs as well as increased performance benefits for Altera Stratix devices and Xilinx Virtex-II Pro devices.
This Synplify Pro 7.3 software release also features automatic gated clock conversion, eliminating the time-consuming task of translating ASIC-based gated-clock elements into FPGA-based clock-enable structures. Additionally, it also offers added support for Xilinx COREgen software and Altera clear box models, providing better timing estimation for IP blocks.
Most FPGA synthesis tools optimise for area or performance, but do not provide the ability to optimise for area once the speed goal is met at a global level. However, using the Synplify Pro software, designers are able to specify a timing frequency on their clocks, and once that frequency is met, the software automatically optimises for less area, while continuing to meet the user's performance targets. Synplicity believes this approach to synthesis enables optimal area reduction resulting in lower device costs.
The software now also features automated register re-timing support for Actel's ProASIC and ProASIC Plus device families. With re-timing, registers are automatically moved within combinatorial logic of the design to improve circuit performance. Here Actel device users can expect to experience an average of more than 15% performance improvements compared to previous releases without re-timing. It also supports Xilinx and Altera devices.
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