Synplicity has enhanced its Identify RTL debugging software with new features to extend its capabilities for FPGA and ASIC prototype hardware debugging. According to the company, the Identify 2.0 software now features a fast and safe incremental flow for Xilinx FPGAs that allows designers to first debug specific signals in their hardware and then change those signals in a matter of minutes, thereby enabling a realtime, debug-centric verification approach.
This new RTL incremental flow allows the available signals for incremental debug to be automatically correlated back to the original RTL source code, taking the guesswork out of FPGA hardware debugging. This latest software also includes support for multiple sample clock views in a single debugger and an improved user interface with a debug project manager, making the tool able to handle complex designs in a more manageable way.
One of the biggest problems with existing hardware debugging solutions is that when designers are not able to find the source of errors, they are forced to run multiple iterations of synthesis and debug insertion. This problem exists because it is difficult for designers to find errors in the post place and route netlist, often because the signal names have changed and there is no way to associate them back to the original RTL source. Because designers are forced to resynthesize the design and go through place and route again, several hours are added to every debug iteration.
"FPGA designers have a huge advantage due to the ability to switch to hardware-based verification early," said Ken McElvain, chief technical officer, Synplicity. "The rapid increase in FPGA design size and complexity has threatened the productivity advantage of FPGA hardware-based verification by increasing the debug cycle time and making it harder to correlate post-synthesis signals with the original RTL design. With Identify 2.0 software designers have RTL visibility into hardware and fast incremental change in the signals that are monitored, avoiding place and route cycles in design debug. This efficient debug-centric verification flow will yield a significant advantage for both ASIC prototypers and FPGA designers who are trying to reach their markets quickly."
The latest version of the Identify 2.0 software also includes a multiple sample clock feature and an improved user interface. Both the instrumentor and debugger software are now available for Redhat Linux 7.2, 7.3 and 8.0 as well as Windows 2000 and XP Professional platforms. The instrumentor software is also available on Solaris 7, 8, and 9 platforms.
For more information contact Franco Giangregorio, Parsec, 012 349 2282, [email protected]
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