Versatile programmable timing devices

28 July 2004 DSP, Micros & Memory

A family of highly versatile programmable timing devices that target a wide range of applications in the communications, storage, digital consumer and industrial markets has been released by IDT. The VersaTime product family represents a complete portfolio of programmable skew and zero delay buffers with non-volatile programming capability, allowing customers to consolidate and replace the large number of dedicated fixed function clock devices currently used to build timing networks. The chips also offer an IEEE 1149.1a compliant JTAG interface that not only enables its inclusion in design-for-test (DFT) infrastructure but also supports device programming within the same scan chain. The clocks achieve low cycle-to-cycle jitter of less than 75 ps (p-p max with outputs at same level) and 100 ps (p-p max with outputs at different levels).

Memec SA, 011 897 8600

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