World's smallest one-gigabit silicon memory

Electronics Technology

1 June 2005 Electronics Technology

Matrix Semiconductor claims to have developed the world's smallest one-gigabit silicon memory at 31 mm², the development of which was based on two technology breakthroughs in three-dimensional semiconductor design: Hybrid Scaling and the Segmented Wordline architecture. Unique to a 3D integrated circuit, Hybrid Scaling is the combination of different process geometries within the layers of a 3D circuit. Matrix' first use of Hybrid Scaling features base logic layers manufactured at 150 nm rules and subsequent memory layers at 130 nm rules. This allows Matrix to shorten its development time and achieve faster time-to-market by increasing the number of memory bits possible on top of a given logic array. Segmented Wordline architecture minimises the effect of non-memory logic circuitry on silicon utilisation. In traditional memory designs, the amount of silicon not used in the memory array lowers the overall manufacturing efficiency of the memory chip. Matrix's three-dimensional approach alleviates this problem by building the memory array on top of the logic circuitry. The architecture results in a far more efficient use of silicon, reducing the die's area by nearly 25% says Matrix.

www.matrixsemi.com

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World's smallest one-gigabit silicon memory

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