Lattice Semiconductor has launched what it says is a new class of crossover programmable logic device that supports applications that traditionally have been addressed either by high density CPLDs or low capacity FPGAs, but with a more comprehensive and cost-effective architecture and technology. The MachXO256 and MachXO640 are the first two members of the company's new MachXO family. With 130 nm nonvolatile embedded Flash process technology, and the use of an industry-standard four-input look-up table approach for logic implementation, the company claims the new devices provide designers with up to 50% lower cost per logic function, yet deliver a dramatic increase in features. Lattice has also added to all family members: distributed memory, a low standby power sleep mode and the ability to transparently update logic configurations through its unique TransFR technology. Support for embedded block RAM and PLL clock circuitry, as well as PCI and LVDS I/O has been added to the larger family members, providing functionality typically found only in traditional FPGA architectures.
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